Commit 0449726b authored Aug 25, 2025 by Timur Kristóf Committed by Alex Deucher Sep 15, 2025

drm/amd/display: Keep PLL0 running on DCE 6.0 and 6.4



DC can turn off the display clock when no displays are connected
or when all displays are off, for reference see:
- dce*_validate_bandwidth

DC also assumes that the DP clock is always on and never powers
it down, for reference see:
- dce110_clock_source_power_down

In case of DCE 6.0 and 6.4, PLL0 is the clock source for both
the engine clock and DP clock, for reference see:
- radeon_atom_pick_pll
- atombios_crtc_set_disp_eng_pll

Therefore, PLL0 should be always kept running on DCE 6.0 and 6.4.
This commit achieves that by ensuring that by setting the display
clock to the corresponding value in low power state instead of
zero.

This fixes a page flip timeout on SI with DC which happens when
all connected displays are blanked.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent 489f0f60

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

+10 −1

Original line number	Diff line number	Diff line
		@@ -881,7 +881,16 @@ static enum dc_status dce60_validate_bandwidth(
		context->bw_ctx.bw.dce.dispclk_khz = 681000;
		context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;
		} else {
		/* On DCE 6.0 and 6.4 the PLL0 is both the display engine clock and
		* the DP clock, and shouldn't be turned off. Just select the display
		* clock value from its low power mode.
		*/
		if (dc->ctx->dce_version == DCE_VERSION_6_0 \|\|
		dc->ctx->dce_version == DCE_VERSION_6_4)
		context->bw_ctx.bw.dce.dispclk_khz = 352000;
		else
		context->bw_ctx.bw.dce.dispclk_khz = 0;

		context->bw_ctx.bw.dce.yclk_khz = 0;
		}