Commit 044feb8e authored by Likun Gao's avatar Likun Gao Committed by Alex Deucher
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drm/amdgpu: fix active rb and cu number for gfx12 



Correct the algorithm of active CU and RB to bypass
the disabled SA for gfx12.

Signed-off-by: default avatarLikun Gao <Likun.Gao@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 56159fff

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

+55 −26
Original line number Diff line number Diff line
@@ -1354,44 +1354,70 @@ static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 
	WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data);

}



static u32 gfx_v12_0_get_rb_active_bitmap(struct amdgpu_device *adev)

static u32 gfx_v12_0_get_sa_active_bitmap(struct amdgpu_device *adev)

{

	u32 data, mask;

	u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask;



	gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_CC_GC_SA_UNIT_DISABLE);

	gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask,

					    GRBM_CC_GC_SA_UNIT_DISABLE,

					    SA_DISABLE);

	gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_GC_USER_SA_UNIT_DISABLE);

	gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask,

						 GRBM_GC_USER_SA_UNIT_DISABLE,

						 SA_DISABLE);

	sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *

					    adev->gfx.config.max_shader_engines);



	data = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE);

	data |= RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE);

	return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask));

}



	data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;

	data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;

static u32 gfx_v12_0_get_rb_active_bitmap(struct amdgpu_device *adev)

{

	u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask;

	u32 rb_mask;



	mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /

					 adev->gfx.config.max_sh_per_se);

	gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE);

	gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask,

					    CC_RB_BACKEND_DISABLE,

					    BACKEND_DISABLE);

	gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE);

	gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask,

						 GC_USER_RB_BACKEND_DISABLE,

						 BACKEND_DISABLE);

	rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se *

					    adev->gfx.config.max_shader_engines);



	return (~data) & mask;

	return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask));

}



static void gfx_v12_0_setup_rb(struct amdgpu_device *adev)

{

	int i, j;

	u32 data;

	u32 active_rbs = 0;

	u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /

				     adev->gfx.config.max_sh_per_se;

	u32 rb_bitmap_width_per_sa;

	u32 max_sa;

	u32 active_sa_bitmap;

	u32 global_active_rb_bitmap;

	u32 active_rb_bitmap = 0;

	u32 i;



	mutex_lock(&adev->grbm_idx_mutex);

	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

			gfx_v12_0_select_se_sh(adev, i, j, 0xffffffff, 0);

			data = gfx_v12_0_get_rb_active_bitmap(adev);

			active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *

					       rb_bitmap_width_per_sh);

		}

	/* query sa bitmap from SA_UNIT_DISABLE registers */

	active_sa_bitmap = gfx_v12_0_get_sa_active_bitmap(adev);

	/* query rb bitmap from RB_BACKEND_DISABLE registers */

	global_active_rb_bitmap = gfx_v12_0_get_rb_active_bitmap(adev);



	/* generate active rb bitmap according to active sa bitmap */

	max_sa = adev->gfx.config.max_shader_engines *

		 adev->gfx.config.max_sh_per_se;

	rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se /

				 adev->gfx.config.max_sh_per_se;

	for (i = 0; i < max_sa; i++) {

		if (active_sa_bitmap & (1 << i))

			active_rb_bitmap |= (0x3 << (i * rb_bitmap_width_per_sa));

	}

	gfx_v12_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);

	mutex_unlock(&adev->grbm_idx_mutex);



	adev->gfx.config.backend_enable_mask = active_rbs;

	adev->gfx.config.num_rbs = hweight32(active_rbs);

	active_rb_bitmap |= global_active_rb_bitmap;

	adev->gfx.config.backend_enable_mask = active_rb_bitmap;

	adev->gfx.config.num_rbs = hweight32(active_rb_bitmap);

}



#define LDS_APP_BASE           0x1
@@ -4832,6 +4858,9 @@ static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 
	mutex_lock(&adev->grbm_idx_mutex);

	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

			bitmap = i * adev->gfx.config.max_sh_per_se + j;

			if (!((gfx_v12_0_get_sa_active_bitmap(adev) >> bitmap) & 1))

				continue;

			mask = 1;

			counter = 0;

			gfx_v12_0_select_se_sh(adev, i, j, 0xffffffff, 0);