Commit 0468df46 authored by Frank Li's avatar Frank Li Committed by Shawn Guo
Browse files

arm64: dts: imx8qm-mek: add fec2 support 



Add fec2 support.

Signed-off-by: default avatarFrank Li <Frank.Li@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 6e7e34a2

arch/arm64/boot/dts/freescale/imx8qm-mek.dts

+40 −0
Original line number Diff line number Diff line
@@ -40,6 +40,15 @@ reg_usdhc2_vmmc: usdhc2-vmmc { 
		enable-active-high;

	};



	reg_fec2_supply: regulator-fec2-nvcc {

		compatible = "regulator-fixed";

		regulator-name = "fec2_nvcc";

		regulator-min-microvolt = <1800000>;

		regulator-max-microvolt = <1800000>;

		gpio = <&max7322 0 GPIO_ACTIVE_HIGH>;

		enable-active-high;

	};



	reg_can01_en: regulator-can01-gen {

		compatible = "regulator-fixed";

		regulator-name = "can01-en";
@@ -334,6 +343,19 @@ ethphy1: ethernet-phy@1 { 
	};

};



&fec2 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_fec2>;

	phy-mode = "rgmii-txid";

	phy-handle = <&ethphy1>;

	phy-supply = <&reg_fec2_supply>;

	nvmem-cells = <&fec_mac1>;

	nvmem-cell-names = "mac-address";

	rx-internal-delay-ps = <2000>;

	fsl,magic-packet;

	status = "okay";

};



&usdhc1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_usdhc1>;
@@ -500,6 +522,24 @@ IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 
		>;

	};



	pinctrl_fec2: fec2grp {

		fsl,pins = <

			IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD		0x000014a0

			IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL	0x00000060

			IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC		0x00000060

			IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0		0x00000060

			IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1		0x00000060

			IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2		0x00000060

			IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3		0x00000060

			IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC		0x00000060

			IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL	0x00000060

			IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0		0x00000060

			IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1		0x00000060

			IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2		0x00000060

			IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3		0x00000060

		>;

	};



	pinctrl_flexcan1: flexcan0grp {

		fsl,pins = <

			IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX			0x21