Commit 04703bfd authored by Jerome Brunet's avatar Jerome Brunet Committed by Neil Armstrong
Browse files

drm/meson: dw-hdmi: power up phy on device init 



The phy is not in a useful state right after init. It will become useful,
including for auxiliary function such as CEC or ARC, after the first mode
is set. This is a problem on systems where the display is using another
interface like DSI or CVBS.

This change refactor the init and mode change callback to power up the PHY
on init and leave only what is necessary for mode changes in the related
function. This is enough to fix CEC operation when HDMI display is not
enabled.

Fixes: 3f68be7d ("drm/meson: Add support for HDMI encoder and DW-HDMI bridge + PHY")
Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
Reviewed-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240426160256.3089978-2-jbrunet@baylibre.com


Signed-off-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20240426160256.3089978-2-jbrunet@baylibre.com
parent da85f0aa

drivers/gpu/drm/meson/meson_dw_hdmi.c

+17 −34
Original line number Diff line number Diff line
@@ -384,26 +384,6 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, 
	    dw_hdmi_bus_fmt_is_420(hdmi))

		mode_is_420 = true;



	/* Enable clocks */

	regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0xffff, 0x100);



	/* Bring HDMITX MEM output of power down */

	regmap_update_bits(priv->hhi, HHI_MEM_PD_REG0, 0xff << 8, 0);



	/* Bring out of reset */

	dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_SW_RESET,  0);



	/* Enable internal pixclk, tmds_clk, spdif_clk, i2s_clk, cecclk */

	dw_hdmi_top_write_bits(dw_hdmi, HDMITX_TOP_CLK_CNTL,

			       0x3, 0x3);



	/* Enable cec_clk and hdcp22_tmdsclk_en */

	dw_hdmi_top_write_bits(dw_hdmi, HDMITX_TOP_CLK_CNTL,

			       0x3 << 4, 0x3 << 4);



	/* Enable normal output to PHY */

	dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_BIST_CNTL, BIT(12));



	/* TMDS pattern setup */

	if (mode->clock > 340000 && !mode_is_420) {

		dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01,
@@ -425,20 +405,6 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, 
	/* Setup PHY parameters */

	meson_hdmi_phy_setup_mode(dw_hdmi, mode, mode_is_420);



	/* Setup PHY */

	regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1,

			   0xffff << 16, 0x0390 << 16);



	/* BIT_INVERT */

	if (dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxl-dw-hdmi") ||

	    dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxm-dw-hdmi") ||

	    dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-g12a-dw-hdmi"))

		regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1,

				   BIT(17), 0);

	else

		regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1,

				   BIT(17), BIT(17));



	/* Disable clock, fifo, fifo_wr */

	regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0);
@@ -656,6 +622,23 @@ static void meson_dw_hdmi_init(struct meson_dw_hdmi *meson_dw_hdmi) 
	meson_dw_hdmi->data->top_write(meson_dw_hdmi,

				       HDMITX_TOP_CLK_CNTL, 0xff);



	/* Enable normal output to PHY */

	meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_BIST_CNTL, BIT(12));



	/* Setup PHY */

	regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1,

			   0xffff << 16, 0x0390 << 16);



	/* BIT_INVERT */

	if (dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-gxl-dw-hdmi") ||

	    dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-gxm-dw-hdmi") ||

	    dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-g12a-dw-hdmi"))

		regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1,

				   BIT(17), 0);

	else

		regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1,

				   BIT(17), BIT(17));



	/* Enable HDMI-TX Interrupt */

	meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_INTR_STAT_CLR,

				       HDMITX_TOP_INTR_CORE);