dt-bindings: PCI: s32g: Add NXP S32G PCIe controller

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/nxp,s32g-pcie.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP S32G2xxx/S32G3xxx PCIe Root Complex controller

maintainers:

  - Bogdan Hamciuc <bogdan.hamciuc@nxp.com>

  - Ionut Vicovan <ionut.vicovan@nxp.com>

description:

  This PCIe controller is based on the Synopsys DesignWare PCIe IP.

  The S32G SoC family has two PCIe controllers, which can be configured as

  either Root Complex or Endpoint.

properties:

  compatible:

    oneOf:

      - enum:

          - nxp,s32g2-pcie

      - items:

          - const: nxp,s32g3-pcie

          - const: nxp,s32g2-pcie

  reg:

    maxItems: 6

  reg-names:

    items:

      - const: dbi

      - const: dbi2

      - const: atu

      - const: dma

      - const: ctrl

      - const: config

  interrupts:

    minItems: 1

    maxItems: 2

  interrupt-names:

    items:

      - const: msi

      - const: dma

    minItems: 1

  pcie@0:

    description:

      Describe the S32G Root Port.

    type: object

    $ref: /schemas/pci/pci-pci-bridge.yaml#

    properties:

      reg:

        maxItems: 1

      phys:

        maxItems: 1

    required:

      - reg

      - phys

    unevaluatedProperties: false

required:

  - compatible

  - reg

  - reg-names

  - interrupts

  - interrupt-names

  - ranges

  - pcie@0

allOf:

  - $ref: /schemas/pci/snps,dw-pcie.yaml#

unevaluatedProperties: false

examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/phy/phy.h>

    bus {

        #address-cells = <2>;

        #size-cells = <2>;

        pcie@40400000 {

            compatible = "nxp,s32g3-pcie", "nxp,s32g2-pcie";

            reg = <0x00 0x40400000 0x0 0x00001000>,   /* dbi registers */

                  <0x00 0x40420000 0x0 0x00001000>,   /* dbi2 registers */

                  <0x00 0x40460000 0x0 0x00001000>,   /* atu registers */

                  <0x00 0x40470000 0x0 0x00001000>,   /* dma registers */

                  <0x00 0x40481000 0x0 0x000000f8>,   /* ctrl registers */

                  <0x5f 0xffffe000 0x0 0x00002000>;   /* config space */

            reg-names = "dbi", "dbi2", "atu", "dma", "ctrl", "config";

            dma-coherent;

            #address-cells = <3>;

            #size-cells = <2>;

            device_type = "pci";

            ranges =

                     <0x01000000 0x0 0x00000000 0x5f 0xfffe0000 0x0 0x00010000>,

                     <0x02000000 0x0 0x00000000 0x58 0x00000000 0x0 0x80000000>,

                     <0x02000000 0x1 0x00000000 0x59 0x00000000 0x6 0xfffe0000>;

            bus-range = <0x0 0xff>;

            interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;

            interrupt-names = "msi", "dma";

            #interrupt-cells = <1>;

            interrupt-map-mask = <0 0 0 0x7>;

            interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,

                            <0 0 0 2 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,

                            <0 0 0 3 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,

                            <0 0 0 4 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;

            pcie@0 {

                reg = <0x0 0x0 0x0 0x0 0x0>;

                #address-cells = <3>;

                #size-cells = <2>;

                ranges;

                device_type = "pci";

                phys = <&serdes0 PHY_TYPE_PCIE 0 0>;

            };

        };

    };