Commit 047d1f6a authored by Haridhar Kalvala's avatar Haridhar Kalvala Committed by Rodrigo Vivi
Browse files

drm/xe: Add Wa_14019877138 



Enable Force Dispatch Ends Collection for DG2.

BSpec: 46001
Signed-off-by: default avatarHaridhar Kalvala <haridhar.kalvala@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20231108073351.3998413-1-haridhar.kalvala@intel.com


Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent d7925d04

drivers/gpu/drm/xe/xe_wa.c

+4 −0
Original line number Diff line number Diff line
@@ -677,6 +677,10 @@ static const struct xe_rtp_entry_sr lrc_was[] = { 
	  XE_RTP_RULES(PLATFORM(DG2)),

	  XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE))

	},

	{ XE_RTP_NAME("14019877138"),

	  XE_RTP_RULES(PLATFORM(DG2)),

	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))

	},



	/* PVC */