Unverified Commit 04a2aef5 authored by Jesse Taube's avatar Jesse Taube Committed by Palmer Dabbelt
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RISC-V: fix vector insn load/store width mask 



RVFDQ_FL_FS_WIDTH_MASK should be 3 bits [14-12], shifted down by 12 bits.
Replace GENMASK(3, 0) with GENMASK(2, 0).

Fixes: cd054837 ("riscv: Allocate user's vector context in the first-use trap")
Signed-off-by: default avatarJesse Taube <jesse@rivosinc.com>
Reviewed-by: default avatarCharlie Jenkins <charlie@rivosinc.com>
Link: https://lore.kernel.org/r/20240606182800.415831-1-jesse@rivosinc.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent f2661062

arch/riscv/include/asm/insn.h

+1 −1
Original line number Diff line number Diff line
@@ -145,7 +145,7 @@ 


/* parts of opcode for RVF, RVD and RVQ */

#define RVFDQ_FL_FS_WIDTH_OFF	12

#define RVFDQ_FL_FS_WIDTH_MASK	GENMASK(3, 0)

#define RVFDQ_FL_FS_WIDTH_MASK	GENMASK(2, 0)

#define RVFDQ_FL_FS_WIDTH_W	2

#define RVFDQ_FL_FS_WIDTH_D	3

#define RVFDQ_LS_FS_WIDTH_Q	4