Commit 04a9f176 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'soc-fixes-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 

Pull SoC fixes from Arnd Bergmann:
 "The firmware drivers for ARM SCMI, FF-A and the Tee subsystem, as
  well as the reset controller and cache controller subsystem all see
  small bugfixes for reference ounting errors, ABI correctness, and
  NULL pointer dereferences.

  Similarly, there are multiple reference counting fixes in drivers/soc/
  for vendor specific drivers (rockchips, microchip), while the
  freescale drivers get a fix for a race condition and error handling.

  The devicetree fixes for Rockchips and NXP got held up, so for
  the moment there is only Renesas fixing problesm with SD card
  initialization, a boot hang on one board and incorrect descriptions
  for interrupts and clock registers on some SoCs. The Microchip
  polarfire gets a dts fix for a boot time warning.

  A defconfig fix avoids a warning about a conflicting assignment"

* tag 'soc-fixes-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (21 commits)
  ARM: multi_v7_defconfig: Drop duplicate CONFIG_TI_PRUSS=m
  firmware: arm_scmi: Spelling s/mulit/multi/, s/currenly/currently/
  firmware: arm_scmi: Fix NULL dereference on notify error path
  firmware: arm_scpi: Fix device_node reference leak in probe path
  firmware: arm_ffa: Remove vm_id argument in ffa_rxtx_unmap()
  arm64: dts: renesas: r8a78000: Fix out-of-range SPI interrupt numbers
  arm64: dts: renesas: rzg3s-smarc-som: Set bypass for Versa3 PLL2
  arm64: dts: renesas: r9a09g087: Fix CPG register region sizes
  arm64: dts: renesas: r9a09g077: Fix CPG register region sizes
  arm64: dts: renesas: r9a09g057: Remove wdt{0,2,3} nodes
  arm64: dts: renesas: rzv2-evk-cn15-sd: Add ramp delay for SD0 regulator
  arm64: dts: renesas: rzt2h-n2h-evk: Add ramp delay for SD0 card regulator
  tee: shm: Remove refcounting of kernel pages
  reset: rzg2l-usbphy-ctrl: Check pwrrdy is valid before using it
  soc: fsl: cpm1: qmc: Fix error check for devm_ioremap_resource() in qmc_qe_init_resources()
  soc: fsl: qbman: fix race condition in qman_destroy_fq
  soc: rockchip: grf: Add missing of_node_put() when returning
  cache: ax45mp: Fix device node reference leak in ax45mp_cache_init()
  cache: starfive: fix device node leak in starlink_cache_init()
  riscv: dts: microchip: add can resets to mpfs
  ...
parents c5cb126c df3ef89d

arch/arm/configs/multi_v7_defconfig

+0 −1
Original line number Diff line number Diff line
@@ -279,7 +279,6 @@ CONFIG_TI_CPSW_SWITCHDEV=y 
CONFIG_TI_CPTS=y

CONFIG_TI_KEYSTONE_NETCP=y

CONFIG_TI_KEYSTONE_NETCP_ETHSS=y

CONFIG_TI_PRUSS=m

CONFIG_TI_PRUETH=m

CONFIG_XILINX_EMACLITE=y

CONFIG_SFP=m

arch/arm64/boot/dts/renesas/r8a78000.dtsi

+8 −8
Original line number Diff line number Diff line
@@ -698,7 +698,7 @@ scif0: serial@c0700000 { 
			compatible = "renesas,scif-r8a78000",

				     "renesas,rcar-gen5-scif", "renesas,scif";

			reg = <0 0xc0700000 0 0x40>;

			interrupts = <GIC_SPI 4074 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_ESPI 10 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			status = "disabled";
@@ -708,7 +708,7 @@ scif1: serial@c0704000 { 
			compatible = "renesas,scif-r8a78000",

				     "renesas,rcar-gen5-scif", "renesas,scif";

			reg = <0 0xc0704000 0 0x40>;

			interrupts = <GIC_SPI 4075 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_ESPI 11 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			status = "disabled";
@@ -718,7 +718,7 @@ scif3: serial@c0708000 { 
			compatible = "renesas,scif-r8a78000",

				     "renesas,rcar-gen5-scif", "renesas,scif";

			reg = <0 0xc0708000 0 0x40>;

			interrupts = <GIC_SPI 4076 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_ESPI 12 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			status = "disabled";
@@ -728,7 +728,7 @@ scif4: serial@c070c000 { 
			compatible = "renesas,scif-r8a78000",

				     "renesas,rcar-gen5-scif", "renesas,scif";

			reg = <0 0xc070c000 0 0x40>;

			interrupts = <GIC_SPI 4077 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_ESPI 13 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			status = "disabled";
@@ -738,7 +738,7 @@ hscif0: serial@c0710000 { 
			compatible = "renesas,hscif-r8a78000",

				     "renesas,rcar-gen5-hscif", "renesas,hscif";

			reg = <0 0xc0710000 0 0x60>;

			interrupts = <GIC_SPI 4078 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_ESPI 14 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			status = "disabled";
@@ -748,7 +748,7 @@ hscif1: serial@c0714000 { 
			compatible = "renesas,hscif-r8a78000",

				     "renesas,rcar-gen5-hscif", "renesas,hscif";

			reg = <0 0xc0714000 0 0x60>;

			interrupts = <GIC_SPI 4079 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_ESPI 15 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			status = "disabled";
@@ -758,7 +758,7 @@ hscif2: serial@c0718000 { 
			compatible = "renesas,hscif-r8a78000",

				     "renesas,rcar-gen5-hscif", "renesas,hscif";

			reg = <0 0xc0718000 0 0x60>;

			interrupts = <GIC_SPI 4080 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_ESPI 16 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			status = "disabled";
@@ -768,7 +768,7 @@ hscif3: serial@c071c000 { 
			compatible = "renesas,hscif-r8a78000",

				     "renesas,rcar-gen5-hscif", "renesas,hscif";

			reg = <0 0xc071c000 0 0x60>;

			interrupts = <GIC_SPI 4081 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_ESPI 17 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			status = "disabled";

arch/arm64/boot/dts/renesas/r9a09g057.dtsi

+0 −30
Original line number Diff line number Diff line
@@ -581,16 +581,6 @@ ostm7: timer@12c03000 { 
			status = "disabled";

		};



		wdt0: watchdog@11c00400 {

			compatible = "renesas,r9a09g057-wdt";

			reg = <0 0x11c00400 0 0x400>;

			clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>;

			clock-names = "pclk", "oscclk";

			resets = <&cpg 0x75>;

			power-domains = <&cpg>;

			status = "disabled";

		};



		wdt1: watchdog@14400000 {

			compatible = "renesas,r9a09g057-wdt";

			reg = <0 0x14400000 0 0x400>;
@@ -601,26 +591,6 @@ wdt1: watchdog@14400000 { 
			status = "disabled";

		};



		wdt2: watchdog@13000000 {

			compatible = "renesas,r9a09g057-wdt";

			reg = <0 0x13000000 0 0x400>;

			clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>;

			clock-names = "pclk", "oscclk";

			resets = <&cpg 0x77>;

			power-domains = <&cpg>;

			status = "disabled";

		};



		wdt3: watchdog@13000400 {

			compatible = "renesas,r9a09g057-wdt";

			reg = <0 0x13000400 0 0x400>;

			clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>;

			clock-names = "pclk", "oscclk";

			resets = <&cpg 0x78>;

			power-domains = <&cpg>;

			status = "disabled";

		};



		rtc: rtc@11c00800 {

			compatible = "renesas,r9a09g057-rtca3", "renesas,rz-rtca3";

			reg = <0 0x11c00800 0 0x400>;

arch/arm64/boot/dts/renesas/r9a09g077.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -974,8 +974,8 @@ mii_conv3: mii-conv@3 { 


		cpg: clock-controller@80280000 {

			compatible = "renesas,r9a09g077-cpg-mssr";

			reg = <0 0x80280000 0 0x1000>,

			      <0 0x81280000 0 0x9000>;

			reg = <0 0x80280000 0 0x10000>,

			      <0 0x81280000 0 0x10000>;

			clocks = <&extal_clk>;

			clock-names = "extal";

			#clock-cells = <2>;

arch/arm64/boot/dts/renesas/r9a09g087.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -977,8 +977,8 @@ mii_conv3: mii-conv@3 { 


		cpg: clock-controller@80280000 {

			compatible = "renesas,r9a09g087-cpg-mssr";

			reg = <0 0x80280000 0 0x1000>,

			      <0 0x81280000 0 0x9000>;

			reg = <0 0x80280000 0 0x10000>,

			      <0 0x81280000 0 0x10000>;

			clocks = <&extal_clk>;

			clock-names = "extal";

			#clock-cells = <2>;