Commit 04b1deb8 authored by Bjorn Andersson's avatar Bjorn Andersson
Browse files

Merge branch '20240430-a750-raytracing-v3-2-7f57c5ac082d@gmail.com' into drivers-for-6.11

Merge SMEM and SCM patches related to GPU features through a topic
branch to make it possible to share these with the msm-next DRM tree.
parents 75287992 81bbb2b8
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+14 −0
Original line number Diff line number Diff line
@@ -1393,6 +1393,20 @@ int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val,
}
EXPORT_SYMBOL_GPL(qcom_scm_lmh_dcvsh);

int qcom_scm_gpu_init_regs(u32 gpu_req)
{
	struct qcom_scm_desc desc = {
		.svc = QCOM_SCM_SVC_GPU,
		.cmd = QCOM_SCM_SVC_GPU_INIT_REGS,
		.arginfo = QCOM_SCM_ARGS(1),
		.args[0] = gpu_req,
		.owner = ARM_SMCCC_OWNER_SIP,
	};

	return qcom_scm_call(__scm->dev, &desc, NULL);
}
EXPORT_SYMBOL_GPL(qcom_scm_gpu_init_regs);

static int qcom_scm_find_dload_address(struct device *dev, u64 *addr)
{
	struct device_node *tcsr;
+3 −0
Original line number Diff line number Diff line
@@ -138,6 +138,9 @@ int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc,
#define QCOM_SCM_WAITQ_RESUME			0x02
#define QCOM_SCM_WAITQ_GET_WQ_CTX		0x03

#define QCOM_SCM_SVC_GPU			0x28
#define QCOM_SCM_SVC_GPU_INIT_REGS		0x01

/* common error codes */
#define QCOM_SCM_V2_EBUSY	-12
#define QCOM_SCM_ENOMEM		-5
+33 −0
Original line number Diff line number Diff line
@@ -795,6 +795,39 @@ int qcom_smem_get_soc_id(u32 *id)
}
EXPORT_SYMBOL_GPL(qcom_smem_get_soc_id);

/**
 * qcom_smem_get_feature_code() - return the feature code
 * @code: On success, return the feature code here.
 *
 * Look up the feature code identifier from SMEM and return it.
 *
 * Return: 0 on success, negative errno on failure.
 */
int qcom_smem_get_feature_code(u32 *code)
{
	struct socinfo *info;
	u32 raw_code;

	info = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_HW_SW_BUILD_ID, NULL);
	if (IS_ERR(info))
		return PTR_ERR(info);

	/* This only makes sense for socinfo >= 16 */
	if (__le32_to_cpu(info->fmt) < SOCINFO_VERSION(0, 16))
		return -EOPNOTSUPP;

	raw_code = __le32_to_cpu(info->feature_code);

	/* Ensure the value makes sense */
	if (raw_code > SOCINFO_FC_INT_MAX)
		raw_code = SOCINFO_FC_UNKNOWN;

	*code = raw_code;

	return 0;
}
EXPORT_SYMBOL_GPL(qcom_smem_get_feature_code);

static int qcom_smem_get_sbl_version(struct qcom_smem *smem)
{
	struct smem_header *header;
+0 −8
Original line number Diff line number Diff line
@@ -21,14 +21,6 @@

#include <dt-bindings/arm/qcom,ids.h>

/*
 * SoC version type with major number in the upper 16 bits and minor
 * number in the lower 16 bits.
 */
#define SOCINFO_MAJOR(ver) (((ver) >> 16) & 0xffff)
#define SOCINFO_MINOR(ver) ((ver) & 0xffff)
#define SOCINFO_VERSION(maj, min)  ((((maj) & 0xffff) << 16)|((min) & 0xffff))

/* Helper macros to create soc_id table */
#define qcom_board_id(id) QCOM_ID_ ## id, __stringify(id)
#define qcom_board_id_named(id, name) QCOM_ID_ ## id, (name)
+23 −0
Original line number Diff line number Diff line
@@ -115,6 +115,29 @@ int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val,
int qcom_scm_lmh_profile_change(u32 profile_id);
bool qcom_scm_lmh_dcvsh_available(void);

/*
 * Request TZ to program set of access controlled registers necessary
 * irrespective of any features
 */
#define QCOM_SCM_GPU_ALWAYS_EN_REQ BIT(0)
/*
 * Request TZ to program BCL id to access controlled register when BCL is
 * enabled
 */
#define QCOM_SCM_GPU_BCL_EN_REQ BIT(1)
/*
 * Request TZ to program set of access controlled register for CLX feature
 * when enabled
 */
#define QCOM_SCM_GPU_CLX_EN_REQ BIT(2)
/*
 * Request TZ to program tsense ids to access controlled registers for reading
 * gpu temperature sensors
 */
#define QCOM_SCM_GPU_TSENSE_EN_REQ BIT(3)

int qcom_scm_gpu_init_regs(u32 gpu_req);

#ifdef CONFIG_QCOM_QSEECOM

int qcom_scm_qseecom_app_get_id(const char *app_name, u32 *app_id);
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