Commit 051da77e authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/dsc: add the PPS number to the register content macros 



Improve clarity by specifying the PPS number in the register content
macros. It's easier to notice if macros are being used for the wrong
register.

Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarSuraj Kandpal <suraj.kandpal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/58de57b04ad2da5207f52c56c9e40663aaf16173.1693933849.git.jani.nikula@intel.com
parent 5828681e

drivers/gpu/drm/i915/display/intel_vdsc.c

+73 −73
Original line number Diff line number Diff line
@@ -423,109 +423,109 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) 
	int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);



	/* PPS 0 */

	pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<

		DSC_VER_MIN_SHIFT |

		vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |

		vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;

	pps_val = DSC_PPS0_VER_MAJ | vdsc_cfg->dsc_version_minor <<

		DSC_PPS0_VER_MIN_SHIFT |

		vdsc_cfg->bits_per_component << DSC_PPS0_BPC_SHIFT |

		vdsc_cfg->line_buf_depth << DSC_PPS0_LINE_BUF_DEPTH_SHIFT;

	if (vdsc_cfg->dsc_version_minor == 2) {

		pps_val |= DSC_ALT_ICH_SEL;

		pps_val |= DSC_PPS0_ALT_ICH_SEL;

		if (vdsc_cfg->native_420)

			pps_val |= DSC_NATIVE_420_ENABLE;

			pps_val |= DSC_PPS0_NATIVE_420_ENABLE;

		if (vdsc_cfg->native_422)

			pps_val |= DSC_NATIVE_422_ENABLE;

			pps_val |= DSC_PPS0_NATIVE_422_ENABLE;

	}

	if (vdsc_cfg->block_pred_enable)

		pps_val |= DSC_BLOCK_PREDICTION;

		pps_val |= DSC_PPS0_BLOCK_PREDICTION;

	if (vdsc_cfg->convert_rgb)

		pps_val |= DSC_COLOR_SPACE_CONVERSION;

		pps_val |= DSC_PPS0_COLOR_SPACE_CONVERSION;

	if (vdsc_cfg->simple_422)

		pps_val |= DSC_422_ENABLE;

		pps_val |= DSC_PPS0_422_ENABLE;

	if (vdsc_cfg->vbr_enable)

		pps_val |= DSC_VBR_ENABLE;

		pps_val |= DSC_PPS0_VBR_ENABLE;

	drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val);

	intel_dsc_pps_write(crtc_state, 0, pps_val);



	/* PPS 1 */

	pps_val = DSC_BPP(vdsc_cfg->bits_per_pixel);

	pps_val = DSC_PPS1_BPP(vdsc_cfg->bits_per_pixel);

	drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val);

	intel_dsc_pps_write(crtc_state, 1, pps_val);



	/* PPS 2 */

	pps_val = DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |

		DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);

	pps_val = DSC_PPS2_PIC_HEIGHT(vdsc_cfg->pic_height) |

		DSC_PPS2_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);

	drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val);

	intel_dsc_pps_write(crtc_state, 2, pps_val);



	/* PPS 3 */

	pps_val = DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |

		DSC_SLICE_WIDTH(vdsc_cfg->slice_width);

	pps_val = DSC_PPS3_SLICE_HEIGHT(vdsc_cfg->slice_height) |

		DSC_PPS3_SLICE_WIDTH(vdsc_cfg->slice_width);

	drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val);

	intel_dsc_pps_write(crtc_state, 3, pps_val);



	/* PPS 4 */

	pps_val = DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |

		DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);

	pps_val = DSC_PPS4_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |

		DSC_PPS4_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);

	drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val);

	intel_dsc_pps_write(crtc_state, 4, pps_val);



	/* PPS 5 */

	pps_val = DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |

		DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);

	pps_val = DSC_PPS5_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |

		DSC_PPS5_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);

	drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val);

	intel_dsc_pps_write(crtc_state, 5, pps_val);



	/* PPS 6 */

	pps_val = DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) |

		DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) |

		DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |

		DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);

	pps_val = DSC_PPS6_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) |

		DSC_PPS6_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) |

		DSC_PPS6_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |

		DSC_PPS6_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);

	drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val);

	intel_dsc_pps_write(crtc_state, 6, pps_val);



	/* PPS 7 */

	pps_val = DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |

		DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);

	pps_val = DSC_PPS7_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |

		DSC_PPS7_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);

	drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val);

	intel_dsc_pps_write(crtc_state, 7, pps_val);



	/* PPS 8 */

	pps_val = DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |

		DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);

	pps_val = DSC_PPS8_FINAL_OFFSET(vdsc_cfg->final_offset) |

		DSC_PPS8_INITIAL_OFFSET(vdsc_cfg->initial_offset);

	drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val);

	intel_dsc_pps_write(crtc_state, 8, pps_val);



	/* PPS 9 */

	pps_val = DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |

		DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);

	pps_val = DSC_PPS9_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |

		DSC_PPS9_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);

	drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val);

	intel_dsc_pps_write(crtc_state, 9, pps_val);



	/* PPS 10 */

	pps_val = DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) |

		DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) |

		DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |

		DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);

	pps_val = DSC_PPS10_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) |

		DSC_PPS10_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) |

		DSC_PPS10_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |

		DSC_PPS10_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);

	drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val);

	intel_dsc_pps_write(crtc_state, 10, pps_val);



	/* PPS 16 */

	pps_val = DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) |

		DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) /

	pps_val = DSC_PPS16_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) |

		DSC_PPS16_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) /

					 vdsc_cfg->slice_width) |

		DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /

		DSC_PPS16_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /

					      vdsc_cfg->slice_height);

	drm_dbg_kms(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val);

	intel_dsc_pps_write(crtc_state, 16, pps_val);



	if (DISPLAY_VER(dev_priv) >= 14) {

		/* PPS 17 */

		pps_val = DSC_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset);

		pps_val = DSC_PPS17_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset);

		drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val);

		intel_dsc_pps_write(crtc_state, 17, pps_val);



		/* PPS 18 */

		pps_val = DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) |

			DSC_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj);

		pps_val = DSC_PPS18_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) |

			DSC_PPS18_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj);

		drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val);

		intel_dsc_pps_write(crtc_state, 18, pps_val);

	}
@@ -857,15 +857,15 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state) 
	/* PPS 0 */

	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 0);



	vdsc_cfg->bits_per_component = (pps_temp & DSC_BPC_MASK) >> DSC_BPC_SHIFT;

	vdsc_cfg->bits_per_component = (pps_temp & DSC_PPS0_BPC_MASK) >> DSC_PPS0_BPC_SHIFT;

	vdsc_cfg->line_buf_depth =

		(pps_temp & DSC_LINE_BUF_DEPTH_MASK) >> DSC_LINE_BUF_DEPTH_SHIFT;

	vdsc_cfg->block_pred_enable = pps_temp & DSC_BLOCK_PREDICTION;

	vdsc_cfg->convert_rgb = pps_temp & DSC_COLOR_SPACE_CONVERSION;

	vdsc_cfg->simple_422 = pps_temp & DSC_422_ENABLE;

	vdsc_cfg->native_422 = pps_temp & DSC_NATIVE_422_ENABLE;

	vdsc_cfg->native_420 = pps_temp & DSC_NATIVE_420_ENABLE;

	vdsc_cfg->vbr_enable = pps_temp & DSC_VBR_ENABLE;

		(pps_temp & DSC_PPS0_LINE_BUF_DEPTH_MASK) >> DSC_PPS0_LINE_BUF_DEPTH_SHIFT;

	vdsc_cfg->block_pred_enable = pps_temp & DSC_PPS0_BLOCK_PREDICTION;

	vdsc_cfg->convert_rgb = pps_temp & DSC_PPS0_COLOR_SPACE_CONVERSION;

	vdsc_cfg->simple_422 = pps_temp & DSC_PPS0_422_ENABLE;

	vdsc_cfg->native_422 = pps_temp & DSC_PPS0_NATIVE_422_ENABLE;

	vdsc_cfg->native_420 = pps_temp & DSC_PPS0_NATIVE_420_ENABLE;

	vdsc_cfg->vbr_enable = pps_temp & DSC_PPS0_VBR_ENABLE;



	/* PPS 1 */

	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 1);
@@ -880,74 +880,74 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state) 
	/* PPS 2 */

	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 2);



	vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PIC_WIDTH_MASK, pps_temp) / num_vdsc_instances;

	vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PIC_HEIGHT_MASK, pps_temp);

	vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PPS2_PIC_WIDTH_MASK, pps_temp) / num_vdsc_instances;

	vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PPS2_PIC_HEIGHT_MASK, pps_temp);



	/* PPS 3 */

	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 3);



	vdsc_cfg->slice_width = REG_FIELD_GET(DSC_SLICE_WIDTH_MASK, pps_temp);

	vdsc_cfg->slice_height = REG_FIELD_GET(DSC_SLICE_HEIGHT_MASK, pps_temp);

	vdsc_cfg->slice_width = REG_FIELD_GET(DSC_PPS3_SLICE_WIDTH_MASK, pps_temp);

	vdsc_cfg->slice_height = REG_FIELD_GET(DSC_PPS3_SLICE_HEIGHT_MASK, pps_temp);



	/* PPS 4 */

	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 4);



	vdsc_cfg->initial_dec_delay = REG_FIELD_GET(DSC_INITIAL_DEC_DELAY_MASK, pps_temp);

	vdsc_cfg->initial_xmit_delay = REG_FIELD_GET(DSC_INITIAL_XMIT_DELAY_MASK, pps_temp);

	vdsc_cfg->initial_dec_delay = REG_FIELD_GET(DSC_PPS4_INITIAL_DEC_DELAY_MASK, pps_temp);

	vdsc_cfg->initial_xmit_delay = REG_FIELD_GET(DSC_PPS4_INITIAL_XMIT_DELAY_MASK, pps_temp);



	/* PPS 5 */

	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 5);



	vdsc_cfg->scale_decrement_interval = REG_FIELD_GET(DSC_SCALE_DEC_INT_MASK, pps_temp);

	vdsc_cfg->scale_increment_interval = REG_FIELD_GET(DSC_SCALE_INC_INT_MASK, pps_temp);

	vdsc_cfg->scale_decrement_interval = REG_FIELD_GET(DSC_PPS5_SCALE_DEC_INT_MASK, pps_temp);

	vdsc_cfg->scale_increment_interval = REG_FIELD_GET(DSC_PPS5_SCALE_INC_INT_MASK, pps_temp);



	/* PPS 6 */

	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 6);



	vdsc_cfg->initial_scale_value = REG_FIELD_GET(DSC_INITIAL_SCALE_VALUE_MASK, pps_temp);

	vdsc_cfg->first_line_bpg_offset = REG_FIELD_GET(DSC_FIRST_LINE_BPG_OFFSET_MASK, pps_temp);

	vdsc_cfg->flatness_min_qp = REG_FIELD_GET(DSC_FLATNESS_MIN_QP_MASK, pps_temp);

	vdsc_cfg->flatness_max_qp = REG_FIELD_GET(DSC_FLATNESS_MAX_QP_MASK, pps_temp);

	vdsc_cfg->initial_scale_value = REG_FIELD_GET(DSC_PPS6_INITIAL_SCALE_VALUE_MASK, pps_temp);

	vdsc_cfg->first_line_bpg_offset = REG_FIELD_GET(DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK, pps_temp);

	vdsc_cfg->flatness_min_qp = REG_FIELD_GET(DSC_PPS6_FLATNESS_MIN_QP_MASK, pps_temp);

	vdsc_cfg->flatness_max_qp = REG_FIELD_GET(DSC_PPS6_FLATNESS_MAX_QP_MASK, pps_temp);



	/* PPS 7 */

	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 7);



	vdsc_cfg->nfl_bpg_offset = REG_FIELD_GET(DSC_NFL_BPG_OFFSET_MASK, pps_temp);

	vdsc_cfg->slice_bpg_offset = REG_FIELD_GET(DSC_SLICE_BPG_OFFSET_MASK, pps_temp);

	vdsc_cfg->nfl_bpg_offset = REG_FIELD_GET(DSC_PPS7_NFL_BPG_OFFSET_MASK, pps_temp);

	vdsc_cfg->slice_bpg_offset = REG_FIELD_GET(DSC_PPS7_SLICE_BPG_OFFSET_MASK, pps_temp);



	/* PPS 8 */

	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 8);



	vdsc_cfg->initial_offset = REG_FIELD_GET(DSC_INITIAL_OFFSET_MASK, pps_temp);

	vdsc_cfg->final_offset = REG_FIELD_GET(DSC_FINAL_OFFSET_MASK, pps_temp);

	vdsc_cfg->initial_offset = REG_FIELD_GET(DSC_PPS8_INITIAL_OFFSET_MASK, pps_temp);

	vdsc_cfg->final_offset = REG_FIELD_GET(DSC_PPS8_FINAL_OFFSET_MASK, pps_temp);



	/* PPS 9 */

	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 9);



	vdsc_cfg->rc_model_size = REG_FIELD_GET(DSC_RC_MODEL_SIZE_MASK, pps_temp);

	vdsc_cfg->rc_model_size = REG_FIELD_GET(DSC_PPS9_RC_MODEL_SIZE_MASK, pps_temp);



	/* PPS 10 */

	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 10);



	vdsc_cfg->rc_quant_incr_limit0 = REG_FIELD_GET(DSC_RC_QUANT_INC_LIMIT0_MASK, pps_temp);

	vdsc_cfg->rc_quant_incr_limit1 = REG_FIELD_GET(DSC_RC_QUANT_INC_LIMIT1_MASK, pps_temp);

	vdsc_cfg->rc_quant_incr_limit0 = REG_FIELD_GET(DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK, pps_temp);

	vdsc_cfg->rc_quant_incr_limit1 = REG_FIELD_GET(DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK, pps_temp);



	/* PPS 16 */

	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 16);



	vdsc_cfg->slice_chunk_size = REG_FIELD_GET(DSC_SLICE_CHUNK_SIZE_MASK, pps_temp);

	vdsc_cfg->slice_chunk_size = REG_FIELD_GET(DSC_PPS16_SLICE_CHUNK_SIZE_MASK, pps_temp);



	if (DISPLAY_VER(i915) >= 14) {

		/* PPS 17 */

		pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 17);



		vdsc_cfg->second_line_bpg_offset = REG_FIELD_GET(DSC_SL_BPG_OFFSET_MASK, pps_temp);

		vdsc_cfg->second_line_bpg_offset = REG_FIELD_GET(DSC_PPS17_SL_BPG_OFFSET_MASK, pps_temp);



		/* PPS 18 */

		pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 18);



		vdsc_cfg->nsl_bpg_offset = REG_FIELD_GET(DSC_NSL_BPG_OFFSET_MASK, pps_temp);

		vdsc_cfg->second_line_offset_adj = REG_FIELD_GET(DSC_SL_OFFSET_ADJ_MASK, pps_temp);

		vdsc_cfg->nsl_bpg_offset = REG_FIELD_GET(DSC_PPS18_NSL_BPG_OFFSET_MASK, pps_temp);

		vdsc_cfg->second_line_offset_adj = REG_FIELD_GET(DSC_PPS18_SL_OFFSET_ADJ_MASK, pps_temp);

	}

}

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

+76 −76
Original line number Diff line number Diff line
@@ -73,115 +73,115 @@ 
#define  ICL_DSC1_PPS(pipe, pps)		_MMIO(_ICL_DSC1_PPS_0(pipe) + ((pps) * 4))



/* PPS 0 */

#define  DSC_NATIVE_422_ENABLE		BIT(23)

#define  DSC_NATIVE_420_ENABLE		BIT(22)

#define  DSC_ALT_ICH_SEL		(1 << 20)

#define  DSC_VBR_ENABLE			(1 << 19)

#define  DSC_422_ENABLE			(1 << 18)

#define  DSC_COLOR_SPACE_CONVERSION	(1 << 17)

#define  DSC_BLOCK_PREDICTION		(1 << 16)

#define  DSC_LINE_BUF_DEPTH_SHIFT	12

#define  DSC_LINE_BUF_DEPTH_MASK	REG_GENMASK(15, 12)

#define  DSC_BPC_SHIFT			8

#define  DSC_BPC_MASK			REG_GENMASK(11, 8)

#define  DSC_VER_MIN_SHIFT		4

#define  DSC_VER_MAJ			(0x1 << 0)

#define   DSC_PPS0_NATIVE_422_ENABLE		BIT(23)

#define   DSC_PPS0_NATIVE_420_ENABLE		BIT(22)

#define   DSC_PPS0_ALT_ICH_SEL			(1 << 20)

#define   DSC_PPS0_VBR_ENABLE			(1 << 19)

#define   DSC_PPS0_422_ENABLE			(1 << 18)

#define   DSC_PPS0_COLOR_SPACE_CONVERSION	(1 << 17)

#define   DSC_PPS0_BLOCK_PREDICTION		(1 << 16)

#define   DSC_PPS0_LINE_BUF_DEPTH_SHIFT		12

#define   DSC_PPS0_LINE_BUF_DEPTH_MASK		REG_GENMASK(15, 12)

#define   DSC_PPS0_BPC_SHIFT			8

#define   DSC_PPS0_BPC_MASK			REG_GENMASK(11, 8)

#define   DSC_PPS0_VER_MIN_SHIFT		4

#define   DSC_PPS0_VER_MAJ			(0x1 << 0)



/* PPS 1 */

#define  DSC_BPP(bpp)				((bpp) << 0)

#define   DSC_PPS1_BPP(bpp)			((bpp) << 0)



/* PPS 2 */

#define  DSC_PIC_WIDTH_MASK		REG_GENMASK(31, 16)

#define  DSC_PIC_HEIGHT_MASK		REG_GENMASK(15, 0)

#define  DSC_PIC_WIDTH(pic_width)	REG_FIELD_PREP(DSC_PIC_WIDTH_MASK, pic_width)

#define  DSC_PIC_HEIGHT(pic_height)	REG_FIELD_PREP(DSC_PIC_HEIGHT_MASK, pic_height)

#define   DSC_PPS2_PIC_WIDTH_MASK		REG_GENMASK(31, 16)

#define   DSC_PPS2_PIC_HEIGHT_MASK		REG_GENMASK(15, 0)

#define   DSC_PPS2_PIC_WIDTH(pic_width)		REG_FIELD_PREP(DSC_PPS2_PIC_WIDTH_MASK, pic_width)

#define   DSC_PPS2_PIC_HEIGHT(pic_height)	REG_FIELD_PREP(DSC_PPS2_PIC_HEIGHT_MASK, pic_height)



/* PPS 3 */

#define  DSC_SLICE_WIDTH_MASK			REG_GENMASK(31, 16)

#define  DSC_SLICE_HEIGHT_MASK			REG_GENMASK(15, 0)

#define  DSC_SLICE_WIDTH(slice_width)		REG_FIELD_PREP(DSC_SLICE_WIDTH_MASK, slice_width)

#define  DSC_SLICE_HEIGHT(slice_height)		REG_FIELD_PREP(DSC_SLICE_HEIGHT_MASK, slice_height)

#define   DSC_PPS3_SLICE_WIDTH_MASK		REG_GENMASK(31, 16)

#define   DSC_PPS3_SLICE_HEIGHT_MASK		REG_GENMASK(15, 0)

#define   DSC_PPS3_SLICE_WIDTH(slice_width)	REG_FIELD_PREP(DSC_PPS3_SLICE_WIDTH_MASK, slice_width)

#define   DSC_PPS3_SLICE_HEIGHT(slice_height)	REG_FIELD_PREP(DSC_PPS3_SLICE_HEIGHT_MASK, slice_height)



/* PPS 4 */

#define  DSC_INITIAL_DEC_DELAY_MASK		REG_GENMASK(31, 16)

#define  DSC_INITIAL_XMIT_DELAY_MASK		REG_GENMASK(9, 0)

#define  DSC_INITIAL_DEC_DELAY(dec_delay)       REG_FIELD_PREP(DSC_INITIAL_DEC_DELAY_MASK, \

#define   DSC_PPS4_INITIAL_DEC_DELAY_MASK	REG_GENMASK(31, 16)

#define   DSC_PPS4_INITIAL_XMIT_DELAY_MASK	REG_GENMASK(9, 0)

#define   DSC_PPS4_INITIAL_DEC_DELAY(dec_delay)	REG_FIELD_PREP(DSC_PPS4_INITIAL_DEC_DELAY_MASK, \

							       dec_delay)

#define  DSC_INITIAL_XMIT_DELAY(xmit_delay)     REG_FIELD_PREP(DSC_INITIAL_XMIT_DELAY_MASK, \

#define   DSC_PPS4_INITIAL_XMIT_DELAY(xmit_delay)	REG_FIELD_PREP(DSC_PPS4_INITIAL_XMIT_DELAY_MASK, \

								       xmit_delay)



/* PPS 5 */

#define  DSC_SCALE_DEC_INT_MASK			REG_GENMASK(27, 16)

#define  DSC_SCALE_INC_INT_MASK			REG_GENMASK(15, 0)

#define  DSC_SCALE_DEC_INT(scale_dec)		REG_FIELD_PREP(DSC_SCALE_DEC_INT_MASK, scale_dec)

#define  DSC_SCALE_INC_INT(scale_inc)		REG_FIELD_PREP(DSC_SCALE_INC_INT_MASK, scale_inc)

#define   DSC_PPS5_SCALE_DEC_INT_MASK		REG_GENMASK(27, 16)

#define   DSC_PPS5_SCALE_INC_INT_MASK		REG_GENMASK(15, 0)

#define   DSC_PPS5_SCALE_DEC_INT(scale_dec)	REG_FIELD_PREP(DSC_PPS5_SCALE_DEC_INT_MASK, scale_dec)

#define   DSC_PPS5_SCALE_INC_INT(scale_inc)	REG_FIELD_PREP(DSC_PPS5_SCALE_INC_INT_MASK, scale_inc)



/* PPS 6 */

#define  DSC_FLATNESS_MAX_QP_MASK		REG_GENMASK(28, 24)

#define  DSC_FLATNESS_MIN_QP_MASK		REG_GENMASK(20, 16)

#define  DSC_FIRST_LINE_BPG_OFFSET_MASK		REG_GENMASK(12, 8)

#define  DSC_INITIAL_SCALE_VALUE_MASK		REG_GENMASK(5, 0)

#define  DSC_FLATNESS_MAX_QP(max_qp)		REG_FIELD_PREP(DSC_FLATNESS_MAX_QP_MASK, max_qp)

#define  DSC_FLATNESS_MIN_QP(min_qp)		REG_FIELD_PREP(DSC_FLATNESS_MIN_QP_MASK, min_qp)

#define  DSC_FIRST_LINE_BPG_OFFSET(offset)	REG_FIELD_PREP(DSC_FIRST_LINE_BPG_OFFSET_MASK, \

#define   DSC_PPS6_FLATNESS_MAX_QP_MASK		REG_GENMASK(28, 24)

#define   DSC_PPS6_FLATNESS_MIN_QP_MASK		REG_GENMASK(20, 16)

#define   DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK	REG_GENMASK(12, 8)

#define   DSC_PPS6_INITIAL_SCALE_VALUE_MASK	REG_GENMASK(5, 0)

#define   DSC_PPS6_FLATNESS_MAX_QP(max_qp)	REG_FIELD_PREP(DSC_PPS6_FLATNESS_MAX_QP_MASK, max_qp)

#define   DSC_PPS6_FLATNESS_MIN_QP(min_qp)	REG_FIELD_PREP(DSC_PPS6_FLATNESS_MIN_QP_MASK, min_qp)

#define   DSC_PPS6_FIRST_LINE_BPG_OFFSET(offset)	REG_FIELD_PREP(DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK, \

								       offset)

#define  DSC_INITIAL_SCALE_VALUE(value)		REG_FIELD_PREP(DSC_INITIAL_SCALE_VALUE_MASK, \

#define   DSC_PPS6_INITIAL_SCALE_VALUE(value)	REG_FIELD_PREP(DSC_PPS6_INITIAL_SCALE_VALUE_MASK, \

							       value)



/* PPS 7 */

#define  DSC_NFL_BPG_OFFSET_MASK		REG_GENMASK(31, 16)

#define  DSC_SLICE_BPG_OFFSET_MASK		REG_GENMASK(15, 0)

#define  DSC_NFL_BPG_OFFSET(bpg_offset)		REG_FIELD_PREP(DSC_NFL_BPG_OFFSET_MASK, bpg_offset)

#define  DSC_SLICE_BPG_OFFSET(bpg_offset)	REG_FIELD_PREP(DSC_SLICE_BPG_OFFSET_MASK, \

#define   DSC_PPS7_NFL_BPG_OFFSET_MASK		REG_GENMASK(31, 16)

#define   DSC_PPS7_SLICE_BPG_OFFSET_MASK	REG_GENMASK(15, 0)

#define   DSC_PPS7_NFL_BPG_OFFSET(bpg_offset)	REG_FIELD_PREP(DSC_PPS7_NFL_BPG_OFFSET_MASK, bpg_offset)

#define   DSC_PPS7_SLICE_BPG_OFFSET(bpg_offset)	REG_FIELD_PREP(DSC_PPS7_SLICE_BPG_OFFSET_MASK, \

							       bpg_offset)

/* PPS 8 */

#define  DSC_INITIAL_OFFSET_MASK		REG_GENMASK(31, 16)

#define  DSC_FINAL_OFFSET_MASK			REG_GENMASK(15, 0)

#define  DSC_INITIAL_OFFSET(initial_offset)	REG_FIELD_PREP(DSC_INITIAL_OFFSET_MASK, \

#define   DSC_PPS8_INITIAL_OFFSET_MASK		REG_GENMASK(31, 16)

#define   DSC_PPS8_FINAL_OFFSET_MASK		REG_GENMASK(15, 0)

#define   DSC_PPS8_INITIAL_OFFSET(initial_offset)	REG_FIELD_PREP(DSC_PPS8_INITIAL_OFFSET_MASK, \

								       initial_offset)

#define  DSC_FINAL_OFFSET(final_offset)		REG_FIELD_PREP(DSC_FINAL_OFFSET_MASK, \

#define   DSC_PPS8_FINAL_OFFSET(final_offset)	REG_FIELD_PREP(DSC_PPS8_FINAL_OFFSET_MASK, \

							       final_offset)



/* PPS 9 */

#define  DSC_RC_EDGE_FACTOR_MASK		REG_GENMASK(19, 16)

#define  DSC_RC_MODEL_SIZE_MASK			REG_GENMASK(15, 0)

#define  DSC_RC_EDGE_FACTOR(rc_edge_fact)	REG_FIELD_PREP(DSC_RC_EDGE_FACTOR_MASK, \

#define   DSC_PPS9_RC_EDGE_FACTOR_MASK		REG_GENMASK(19, 16)

#define   DSC_PPS9_RC_MODEL_SIZE_MASK		REG_GENMASK(15, 0)

#define   DSC_PPS9_RC_EDGE_FACTOR(rc_edge_fact)	REG_FIELD_PREP(DSC_PPS9_RC_EDGE_FACTOR_MASK, \

							       rc_edge_fact)

#define  DSC_RC_MODEL_SIZE(rc_model_size)	REG_FIELD_PREP(DSC_RC_MODEL_SIZE_MASK, \

#define   DSC_PPS9_RC_MODEL_SIZE(rc_model_size)	REG_FIELD_PREP(DSC_PPS9_RC_MODEL_SIZE_MASK, \

							       rc_model_size)



/* PPS 10 */

#define  DSC_RC_TGT_OFF_LOW_MASK			REG_GENMASK(23, 20)

#define  DSC_RC_TGT_OFF_HIGH_MASK			REG_GENMASK(19, 16)

#define  DSC_RC_QUANT_INC_LIMIT1_MASK			REG_GENMASK(12, 8)

#define  DSC_RC_QUANT_INC_LIMIT0_MASK			REG_GENMASK(4, 0)

#define  DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low)		REG_FIELD_PREP(DSC_RC_TGT_OFF_LOW_MASK, \

#define   DSC_PPS10_RC_TGT_OFF_LOW_MASK		REG_GENMASK(23, 20)

#define   DSC_PPS10_RC_TGT_OFF_HIGH_MASK	REG_GENMASK(19, 16)

#define   DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK	REG_GENMASK(12, 8)

#define   DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK	REG_GENMASK(4, 0)

#define   DSC_PPS10_RC_TARGET_OFF_LOW(rc_tgt_off_low)	REG_FIELD_PREP(DSC_PPS10_RC_TGT_OFF_LOW_MASK, \

								       rc_tgt_off_low)

#define  DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high)	REG_FIELD_PREP(DSC_RC_TGT_OFF_HIGH_MASK, \

#define   DSC_PPS10_RC_TARGET_OFF_HIGH(rc_tgt_off_high)	REG_FIELD_PREP(DSC_PPS10_RC_TGT_OFF_HIGH_MASK, \

								       rc_tgt_off_high)

#define  DSC_RC_QUANT_INC_LIMIT1(lim)		REG_FIELD_PREP(DSC_RC_QUANT_INC_LIMIT1_MASK, lim)

#define  DSC_RC_QUANT_INC_LIMIT0(lim)		REG_FIELD_PREP(DSC_RC_QUANT_INC_LIMIT0_MASK, lim)

#define   DSC_PPS10_RC_QUANT_INC_LIMIT1(lim)	REG_FIELD_PREP(DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK, lim)

#define   DSC_PPS10_RC_QUANT_INC_LIMIT0(lim)	REG_FIELD_PREP(DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK, lim)



/* PPS 16 */

#define  DSC_SLICE_ROW_PR_FRME_MASK			REG_GENMASK(31, 20)

#define  DSC_SLICE_PER_LINE_MASK			REG_GENMASK(18, 16)

#define  DSC_SLICE_CHUNK_SIZE_MASK			REG_GENMASK(15, 0)

#define  DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame)	REG_FIELD_PREP(DSC_SLICE_ROW_PR_FRME_MASK, \

#define   DSC_PPS16_SLICE_ROW_PR_FRME_MASK	REG_GENMASK(31, 20)

#define   DSC_PPS16_SLICE_PER_LINE_MASK		REG_GENMASK(18, 16)

#define   DSC_PPS16_SLICE_CHUNK_SIZE_MASK	REG_GENMASK(15, 0)

#define   DSC_PPS16_SLICE_ROW_PER_FRAME(slice_row_per_frame)	REG_FIELD_PREP(DSC_PPS16_SLICE_ROW_PR_FRME_MASK, \

									       slice_row_per_frame)

#define  DSC_SLICE_PER_LINE(slice_per_line)		REG_FIELD_PREP(DSC_SLICE_PER_LINE_MASK, \

#define   DSC_PPS16_SLICE_PER_LINE(slice_per_line)		REG_FIELD_PREP(DSC_PPS16_SLICE_PER_LINE_MASK, \

									       slice_per_line)

#define  DSC_SLICE_CHUNK_SIZE(slice_chunk_size)		REG_FIELD_PREP(DSC_SLICE_CHUNK_SIZE_MASK, \

#define   DSC_PPS16_SLICE_CHUNK_SIZE(slice_chunk_size)		REG_FIELD_PREP(DSC_PPS16_SLICE_CHUNK_SIZE_MASK, \

									       slice_chunk_size)



/* PPS 17 (MTL+) */

#define DSC_SL_BPG_OFFSET_MASK			REG_GENMASK(31, 27)

#define DSC_SL_BPG_OFFSET(offset)		REG_FIELD_PREP(DSC_SL_BPG_OFFSET_MASK, offset)

#define   DSC_PPS17_SL_BPG_OFFSET_MASK		REG_GENMASK(31, 27)

#define   DSC_PPS17_SL_BPG_OFFSET(offset)	REG_FIELD_PREP(DSC_PPS17_SL_BPG_OFFSET_MASK, offset)



/* PPS 18 (MTL+) */

#define DSC_NSL_BPG_OFFSET_MASK			REG_GENMASK(31, 16)

#define DSC_SL_OFFSET_ADJ_MASK			REG_GENMASK(15, 0)

#define DSC_NSL_BPG_OFFSET(offset)		REG_FIELD_PREP(DSC_NSL_BPG_OFFSET_MASK, offset)

#define DSC_SL_OFFSET_ADJ(offset)		REG_FIELD_PREP(DSC_SL_OFFSET_ADJ_MASK, offset)

#define   DSC_PPS18_NSL_BPG_OFFSET_MASK		REG_GENMASK(31, 16)

#define   DSC_PPS18_SL_OFFSET_ADJ_MASK		REG_GENMASK(15, 0)

#define   DSC_PPS18_NSL_BPG_OFFSET(offset)	REG_FIELD_PREP(DSC_PPS18_NSL_BPG_OFFSET_MASK, offset)

#define   DSC_PPS18_SL_OFFSET_ADJ(offset)	REG_FIELD_PREP(DSC_PPS18_SL_OFFSET_ADJ_MASK, offset)



/* Icelake Rate Control Buffer Threshold Registers */

#define DSCA_RC_BUF_THRESH_0			_MMIO(0x6B230)