Commit 056d76f7 authored by Sebastian Reichel's avatar Sebastian Reichel Committed by Neil Armstrong
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drm/panel: sitronix-st7789v: fix sync flags for t28cp45tn89 



I planned to set the polarity of horizontal and vertical sync, but
accidentally described vertical sync twice with different polarity
instead.

Note, that there is no functional change, because the driver only
makes use of DRM_MODE_FLAG_P[HV]SYNC to divert from the default
active-low polarity.

Reported-by: default avatarLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Closes: https://lore.kernel.org/all/20250923132616.GH20765@pendragon.ideasonboard.com/


Fixes: a411558c ("drm/panel: sitronix-st7789v: add Inanbo T28CP45TN89 support")
Reviewed-by: default avatarLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: default avatarMarek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: default avatarSebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20251001-t28cp45tn89-fix-v2-1-67fe8e3046ca@collabora.com
parent 9e8b3201

drivers/gpu/drm/panel/panel-sitronix-st7789v.c

+6 −1
Original line number Diff line number Diff line
@@ -249,6 +249,11 @@ static const struct drm_display_mode default_mode = { 
	.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,

};



/*

 * The mode data for this panel has been reverse engineered without access

 * to the panel datasheet / manual. Using DRM_MODE_FLAG_PHSYNC like all

 * other panels results in garbage data on the display.

 */

static const struct drm_display_mode t28cp45tn89_mode = {

	.clock = 6008,

	.hdisplay = 240,
@@ -261,7 +266,7 @@ static const struct drm_display_mode t28cp45tn89_mode = { 
	.vtotal = 320 + 8 + 4 + 4,

	.width_mm = 43,

	.height_mm = 57,

	.flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC,

	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC,

};



static const struct drm_display_mode et028013dma_mode = {