Commit 057ad0ef authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-next-7.1-2026-03-04' of https://gitlab.freedesktop.org/agd5f/linux into drm-next 

amd-drm-next-7.1-2026-03-04:

amdgpu:
- FAMS2 updates
- Refactor DC I2C
- Rework ttm handling to allow for multiple engines
- UserQ updates
- Ring reset improvements
- DC DCE 6.x cleanups
- DC support for NUTMEG and TRAVIS DP bridges
- Enable DC by default on CIK APUs
- Add DCN 4.2 support
- IPS fixes
- Overlay fixes for DCN4
- SDMA Limit updates
- Misc fixes
- RAS updates
- Register access callback rework
- GC 12.1 updates

amdkfd:
- Misc cleanups

UAPI:
- UserQ fence IOCTL parameter size fixes.  The change is backwards compatible on LE, but not BE.
  UserQs are still not considered stable and are disabled by default.

From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patch.msgid.link/20260304213233.1938311-1-alexander.deucher@amd.com


Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parents 17b95278 c5d8df53

drivers/gpu/drm/amd/amdgpu/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -47,7 +47,7 @@ subdir-ccflags-$(CONFIG_DRM_AMDGPU_WERROR) += -Werror 
amdgpu-y := amdgpu_drv.o



# add KMS driver

amdgpu-y += amdgpu_device.o amdgpu_doorbell_mgr.o amdgpu_kms.o \

amdgpu-y += amdgpu_device.o amdgpu_reg_access.o amdgpu_doorbell_mgr.o amdgpu_kms.o \

	amdgpu_atombios.o atombios_crtc.o amdgpu_connectors.o \

	atom.o amdgpu_fence.o amdgpu_ttm.o amdgpu_object.o amdgpu_gart.o \

	amdgpu_encoders.o amdgpu_display.o amdgpu_i2c.o \

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+39 −115
Original line number Diff line number Diff line
@@ -81,6 +81,7 @@ 
#include "amdgpu_sdma.h"

#include "amdgpu_lsdma.h"

#include "amdgpu_nbio.h"

#include "amdgpu_reg_access.h"

#include "amdgpu_hdp.h"

#include "amdgpu_dm.h"

#include "amdgpu_virt.h"
@@ -217,9 +218,7 @@ extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 
extern int amdgpu_async_gfx_ring;

extern int amdgpu_mcbp;

extern int amdgpu_discovery;

extern int amdgpu_mes;

extern int amdgpu_mes_log_enable;

extern int amdgpu_mes_kiq;

extern int amdgpu_uni_mes;

extern int amdgpu_noretry;

extern int amdgpu_force_asic_type;
@@ -680,21 +679,6 @@ void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 
/*

 * Core structure, functions and helpers.

 */

typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);

typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);



typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device*, uint64_t);

typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device*, uint64_t, uint32_t);



typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);

typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);



typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device*, uint64_t);

typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device*, uint64_t, uint64_t);



typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);

typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);



struct amdgpu_mmio_remap {

	u32 reg_offset;

	resource_size_t bus_addr;
@@ -791,6 +775,12 @@ struct amd_powerplay { 
					  (rid == 0x01) || \

					  (rid == 0x10))))



enum amdgpu_mqd_update_flag {

       AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE = 1,

       AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE = 2,

       AMDGPU_UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */

};



struct amdgpu_mqd_prop {

	uint64_t mqd_gpu_addr;

	uint64_t hqd_base_gpu_addr;
@@ -811,6 +801,10 @@ struct amdgpu_mqd_prop { 
	uint64_t fence_address;

	bool tmz_queue;

	bool kernel_queue;

	uint32_t *cu_mask;

	uint32_t cu_mask_count;

	uint32_t cu_flags;

	bool is_user_cu_masked;

};



struct amdgpu_mqd {
@@ -906,42 +900,8 @@ struct amdgpu_device { 
	/* protects concurrent MM_INDEX/DATA based register access */

	spinlock_t mmio_idx_lock;

	struct amdgpu_mmio_remap        rmmio_remap;

	/* protects concurrent SMC based register access */

	spinlock_t smc_idx_lock;

	amdgpu_rreg_t			smc_rreg;

	amdgpu_wreg_t			smc_wreg;

	/* protects concurrent PCIE register access */

	spinlock_t pcie_idx_lock;

	amdgpu_rreg_t			pcie_rreg;

	amdgpu_wreg_t			pcie_wreg;

	amdgpu_rreg_t			pciep_rreg;

	amdgpu_wreg_t			pciep_wreg;

	amdgpu_rreg_ext_t		pcie_rreg_ext;

	amdgpu_wreg_ext_t		pcie_wreg_ext;

	amdgpu_rreg64_t			pcie_rreg64;

	amdgpu_wreg64_t			pcie_wreg64;

	amdgpu_rreg64_ext_t			pcie_rreg64_ext;

	amdgpu_wreg64_ext_t			pcie_wreg64_ext;

	/* protects concurrent UVD register access */

	spinlock_t uvd_ctx_idx_lock;

	amdgpu_rreg_t			uvd_ctx_rreg;

	amdgpu_wreg_t			uvd_ctx_wreg;

	/* protects concurrent DIDT register access */

	spinlock_t didt_idx_lock;

	amdgpu_rreg_t			didt_rreg;

	amdgpu_wreg_t			didt_wreg;

	/* protects concurrent gc_cac register access */

	spinlock_t gc_cac_idx_lock;

	amdgpu_rreg_t			gc_cac_rreg;

	amdgpu_wreg_t			gc_cac_wreg;

	/* protects concurrent se_cac register access */

	spinlock_t se_cac_idx_lock;

	amdgpu_rreg_t			se_cac_rreg;

	amdgpu_wreg_t			se_cac_wreg;

	/* protects concurrent ENDPOINT (audio) register access */

	spinlock_t audio_endpt_idx_lock;

	amdgpu_block_rreg_t		audio_endpt_rreg;

	amdgpu_block_wreg_t		audio_endpt_wreg;

	/* Indirect register access blocks */

	struct amdgpu_reg_access reg;

	struct amdgpu_doorbell		doorbell;



	/* clock/pll info */
@@ -1297,42 +1257,6 @@ size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 


void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,

			       void *buf, size_t size, bool write);

uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev,

			    uint32_t inst, uint32_t reg_addr, char reg_name[],

			    uint32_t expected_value, uint32_t mask);

uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,

			    uint32_t reg, uint32_t acc_flags);

u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev,

				    u64 reg_addr);

uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev,

				uint32_t reg, uint32_t acc_flags,

				uint32_t xcc_id);

void amdgpu_device_wreg(struct amdgpu_device *adev,

			uint32_t reg, uint32_t v,

			uint32_t acc_flags);

void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev,

				     u64 reg_addr, u32 reg_data);

void amdgpu_device_xcc_wreg(struct amdgpu_device *adev,

			    uint32_t reg, uint32_t v,

			    uint32_t acc_flags,

			    uint32_t xcc_id);

void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,

			     uint32_t reg, uint32_t v, uint32_t xcc_id);

void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);

uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);



u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,

				u32 reg_addr);

u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,

				  u32 reg_addr);

u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev,

				  u64 reg_addr);

void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,

				 u32 reg_addr, u32 reg_data);

void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,

				   u32 reg_addr, u64 reg_data);

void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev,

				   u64 reg_addr, u64 reg_data);

u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev);

bool amdgpu_device_asic_has_dc_support(struct pci_dev *pdev,

				       enum amd_asic_type asic_type);
@@ -1372,28 +1296,30 @@ int emu_soc_asic_init(struct amdgpu_device *adev); 
#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)

#define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst)

#define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst)

#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))

#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))

#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))

#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))

#define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg))

#define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v))

#define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))

#define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))

#define RREG64_PCIE_EXT(reg) adev->pcie_rreg64_ext(adev, (reg))

#define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v))

#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))

#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))

#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))

#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))

#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))

#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))

#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))

#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))

#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))

#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))

#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))

#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))

#define RREG32_PCIE(reg) amdgpu_reg_pcie_rd32(adev, (reg))

#define WREG32_PCIE(reg, v) amdgpu_reg_pcie_wr32(adev, (reg), (v))

#define RREG32_PCIE_PORT(reg) amdgpu_reg_pciep_rd32(adev, (reg))

#define WREG32_PCIE_PORT(reg, v) amdgpu_reg_pciep_wr32(adev, (reg), (v))

#define RREG32_PCIE_EXT(reg) amdgpu_reg_pcie_ext_rd32(adev, (reg))

#define WREG32_PCIE_EXT(reg, v) amdgpu_reg_pcie_ext_wr32(adev, (reg), (v))

#define RREG64_PCIE(reg) amdgpu_reg_pcie_rd64(adev, (reg))

#define WREG64_PCIE(reg, v) amdgpu_reg_pcie_wr64(adev, (reg), (v))

#define RREG64_PCIE_EXT(reg) amdgpu_reg_pcie_ext_rd64(adev, (reg))

#define WREG64_PCIE_EXT(reg, v) amdgpu_reg_pcie_ext_wr64(adev, (reg), (v))

#define RREG32_SMC(reg) amdgpu_reg_smc_rd32(adev, (reg))

#define WREG32_SMC(reg, v) amdgpu_reg_smc_wr32(adev, (reg), (v))

#define RREG32_UVD_CTX(reg) amdgpu_reg_uvd_ctx_rd32(adev, (reg))

#define WREG32_UVD_CTX(reg, v) amdgpu_reg_uvd_ctx_wr32(adev, (reg), (v))

#define RREG32_DIDT(reg) amdgpu_reg_didt_rd32(adev, (reg))

#define WREG32_DIDT(reg, v) amdgpu_reg_didt_wr32(adev, (reg), (v))

#define RREG32_GC_CAC(reg) amdgpu_reg_gc_cac_rd32(adev, (reg))

#define WREG32_GC_CAC(reg, v) amdgpu_reg_gc_cac_wr32(adev, (reg), (v))

#define RREG32_SE_CAC(reg) amdgpu_reg_se_cac_rd32(adev, (reg))

#define WREG32_SE_CAC(reg, v) amdgpu_reg_se_cac_wr32(adev, (reg), (v))

#define RREG32_AUDIO_ENDPT(block, reg) \

	amdgpu_reg_audio_endpt_rd32(adev, (block), (reg))

#define WREG32_AUDIO_ENDPT(block, reg, v) \

	amdgpu_reg_audio_endpt_wr32(adev, (block), (reg), (v))

#define WREG32_P(reg, val, mask)				\

	do {							\

		uint32_t tmp_ = RREG32(reg);			\
@@ -1523,10 +1449,6 @@ void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 
		struct amdgpu_ring *ring);



void amdgpu_device_halt(struct amdgpu_device *adev);

u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,

				u32 reg);

void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,

				u32 reg, u32 v);

struct dma_fence *amdgpu_device_get_gang(struct amdgpu_device *adev);

struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,

					    struct dma_fence *gang);
@@ -1536,6 +1458,8 @@ struct dma_fence *amdgpu_device_enforce_isolation(struct amdgpu_device *adev, 
bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev);

ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu_ring *ring);

ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset);

void amdgpu_sdma_set_vm_pte_scheds(struct amdgpu_device *adev,

				   const struct amdgpu_vm_pte_funcs *vm_pte_funcs);



/* atpx handler */

#if defined(CONFIG_VGA_SWITCHEROO)

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

+5 −1
Original line number Diff line number Diff line
@@ -1439,7 +1439,10 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info, 
		*process_info = info;

	}



	vm->process_info = *process_info;

	if (cmpxchg(&vm->process_info, NULL, *process_info) != NULL) {

		ret = -EINVAL;

		goto already_acquired;

	}



	/* Validate page directory and attach eviction fence */

	ret = amdgpu_bo_reserve(vm->root.bo, true);
@@ -1479,6 +1482,7 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info, 
	amdgpu_bo_unreserve(vm->root.bo);

reserve_pd_fail:

	vm->process_info = NULL;

already_acquired:

	if (info) {

		dma_fence_put(&info->eviction_fence->base);

		*process_info = NULL;

drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c

+2 −0
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ static int amdgpu_benchmark_do_move(struct amdgpu_device *adev, unsigned size, 
	struct dma_fence *fence;

	int i, r;



	mutex_lock(&adev->mman.default_entity.lock);

	stime = ktime_get();

	for (i = 0; i < n; i++) {

		r = amdgpu_copy_buffer(adev, &adev->mman.default_entity,
@@ -49,6 +50,7 @@ static int amdgpu_benchmark_do_move(struct amdgpu_device *adev, unsigned size, 
	}



exit_do_move:

	mutex_unlock(&adev->mman.default_entity.lock);

	etime = ktime_get();

	*time_ms = ktime_ms_delta(etime, stime);

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

+0 −7
Original line number Diff line number Diff line
@@ -84,13 +84,6 @@ static int amdgpu_cs_job_idx(struct amdgpu_cs_parser *p, 
	if (r)

		return r;



	/*

	 * Abort if there is no run queue associated with this entity.

	 * Possibly because of disabled HW IP.

	 */

	if (entity->rq == NULL)

		return -EINVAL;



	/* Check if we can add this IB to some existing job */

	for (i = 0; i < p->gang_size; ++i)

		if (p->entities[i] == entity)