Commit 057e55f3 authored by Rob Clark's avatar Rob Clark
Browse files

drm/msm: Rename msm_gem_address_space -> msm_gem_vm 



Re-aligning naming to better match drm_gpuvm terminology will make
things less confusing at the end of the drm_gpuvm conversion.

This is just rename churn, no functional change.

Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: default avatarRob Clark <robin.clark@oss.qualcomm.com>
Tested-by: default avatarAntonino Maniscalco <antomani103@gmail.com>
Reviewed-by: default avatarAntonino Maniscalco <antomani103@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/661466/
parent fd05abf3

drivers/gpu/drm/msm/adreno/a2xx_gpu.c

+9 −9
Original line number Diff line number Diff line
@@ -113,7 +113,7 @@ static int a2xx_hw_init(struct msm_gpu *gpu) 
	uint32_t *ptr, len;

	int i, ret;



	a2xx_gpummu_params(gpu->aspace->mmu, &pt_base, &tran_error);

	a2xx_gpummu_params(gpu->vm->mmu, &pt_base, &tran_error);



	DBG("%s", gpu->name);
@@ -466,19 +466,19 @@ static struct msm_gpu_state *a2xx_gpu_state_get(struct msm_gpu *gpu) 
	return state;

}



static struct msm_gem_address_space *

a2xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev)

static struct msm_gem_vm *

a2xx_create_vm(struct msm_gpu *gpu, struct platform_device *pdev)

{

	struct msm_mmu *mmu = a2xx_gpummu_new(&pdev->dev, gpu);

	struct msm_gem_address_space *aspace;

	struct msm_gem_vm *vm;



	aspace = msm_gem_address_space_create(mmu, "gpu", SZ_16M,

	vm = msm_gem_vm_create(mmu, "gpu", SZ_16M,

		0xfff * SZ_64K);



	if (IS_ERR(aspace) && !IS_ERR(mmu))

	if (IS_ERR(vm) && !IS_ERR(mmu))

		mmu->funcs->destroy(mmu);



	return aspace;

	return vm;

}



static u32 a2xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
@@ -504,7 +504,7 @@ static const struct adreno_gpu_funcs funcs = { 
#endif

		.gpu_state_get = a2xx_gpu_state_get,

		.gpu_state_put = adreno_gpu_state_put,

		.create_address_space = a2xx_create_address_space,

		.create_vm = a2xx_create_vm,

		.get_rptr = a2xx_get_rptr,

	},

};
@@ -551,7 +551,7 @@ struct msm_gpu *a2xx_gpu_init(struct drm_device *dev) 
	else

		adreno_gpu->registers = a220_registers;



	if (!gpu->aspace) {

	if (!gpu->vm) {

		dev_err(dev->dev, "No memory protection without MMU\n");

		if (!allow_vram_carveout) {

			ret = -ENXIO;

drivers/gpu/drm/msm/adreno/a3xx_gpu.c

+2 −2
Original line number Diff line number Diff line
@@ -526,7 +526,7 @@ static const struct adreno_gpu_funcs funcs = { 
		.gpu_busy = a3xx_gpu_busy,

		.gpu_state_get = a3xx_gpu_state_get,

		.gpu_state_put = adreno_gpu_state_put,

		.create_address_space = adreno_create_address_space,

		.create_vm = adreno_create_vm,

		.get_rptr = a3xx_get_rptr,

	},

};
@@ -581,7 +581,7 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev) 
			goto fail;

	}



	if (!gpu->aspace) {

	if (!gpu->vm) {

		/* TODO we think it is possible to configure the GPU to

		 * restrict access to VRAM carveout.  But the required

		 * registers are unknown.  For now just bail out and

drivers/gpu/drm/msm/adreno/a4xx_gpu.c

+2 −2
Original line number Diff line number Diff line
@@ -645,7 +645,7 @@ static const struct adreno_gpu_funcs funcs = { 
		.gpu_busy = a4xx_gpu_busy,

		.gpu_state_get = a4xx_gpu_state_get,

		.gpu_state_put = adreno_gpu_state_put,

		.create_address_space = adreno_create_address_space,

		.create_vm = adreno_create_vm,

		.get_rptr = a4xx_get_rptr,

	},

	.get_timestamp = a4xx_get_timestamp,
@@ -695,7 +695,7 @@ struct msm_gpu *a4xx_gpu_init(struct drm_device *dev) 


	adreno_gpu->uche_trap_base = 0xffff0000ffff0000ull;



	if (!gpu->aspace) {

	if (!gpu->vm) {

		/* TODO we think it is possible to configure the GPU to

		 * restrict access to VRAM carveout.  But the required

		 * registers are unknown.  For now just bail out and

drivers/gpu/drm/msm/adreno/a5xx_debugfs.c

+2 −2
Original line number Diff line number Diff line
@@ -116,13 +116,13 @@ reset_set(void *data, u64 val) 
	adreno_gpu->fw[ADRENO_FW_PFP] = NULL;



	if (a5xx_gpu->pm4_bo) {

		msm_gem_unpin_iova(a5xx_gpu->pm4_bo, gpu->aspace);

		msm_gem_unpin_iova(a5xx_gpu->pm4_bo, gpu->vm);

		drm_gem_object_put(a5xx_gpu->pm4_bo);

		a5xx_gpu->pm4_bo = NULL;

	}



	if (a5xx_gpu->pfp_bo) {

		msm_gem_unpin_iova(a5xx_gpu->pfp_bo, gpu->aspace);

		msm_gem_unpin_iova(a5xx_gpu->pfp_bo, gpu->vm);

		drm_gem_object_put(a5xx_gpu->pfp_bo);

		a5xx_gpu->pfp_bo = NULL;

	}

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

+11 −11
Original line number Diff line number Diff line
@@ -622,7 +622,7 @@ static int a5xx_ucode_load(struct msm_gpu *gpu) 
			a5xx_gpu->shadow = msm_gem_kernel_new(gpu->dev,

				sizeof(u32) * gpu->nr_rings,

				MSM_BO_WC | MSM_BO_MAP_PRIV,

				gpu->aspace, &a5xx_gpu->shadow_bo,

				gpu->vm, &a5xx_gpu->shadow_bo,

				&a5xx_gpu->shadow_iova);



			if (IS_ERR(a5xx_gpu->shadow))
@@ -1042,22 +1042,22 @@ static void a5xx_destroy(struct msm_gpu *gpu) 
	a5xx_preempt_fini(gpu);



	if (a5xx_gpu->pm4_bo) {

		msm_gem_unpin_iova(a5xx_gpu->pm4_bo, gpu->aspace);

		msm_gem_unpin_iova(a5xx_gpu->pm4_bo, gpu->vm);

		drm_gem_object_put(a5xx_gpu->pm4_bo);

	}



	if (a5xx_gpu->pfp_bo) {

		msm_gem_unpin_iova(a5xx_gpu->pfp_bo, gpu->aspace);

		msm_gem_unpin_iova(a5xx_gpu->pfp_bo, gpu->vm);

		drm_gem_object_put(a5xx_gpu->pfp_bo);

	}



	if (a5xx_gpu->gpmu_bo) {

		msm_gem_unpin_iova(a5xx_gpu->gpmu_bo, gpu->aspace);

		msm_gem_unpin_iova(a5xx_gpu->gpmu_bo, gpu->vm);

		drm_gem_object_put(a5xx_gpu->gpmu_bo);

	}



	if (a5xx_gpu->shadow_bo) {

		msm_gem_unpin_iova(a5xx_gpu->shadow_bo, gpu->aspace);

		msm_gem_unpin_iova(a5xx_gpu->shadow_bo, gpu->vm);

		drm_gem_object_put(a5xx_gpu->shadow_bo);

	}
@@ -1457,7 +1457,7 @@ static int a5xx_crashdumper_init(struct msm_gpu *gpu, 
		struct a5xx_crashdumper *dumper)

{

	dumper->ptr = msm_gem_kernel_new(gpu->dev,

		SZ_1M, MSM_BO_WC, gpu->aspace,

		SZ_1M, MSM_BO_WC, gpu->vm,

		&dumper->bo, &dumper->iova);



	if (!IS_ERR(dumper->ptr))
@@ -1557,7 +1557,7 @@ static void a5xx_gpu_state_get_hlsq_regs(struct msm_gpu *gpu, 


	if (a5xx_crashdumper_run(gpu, &dumper)) {

		kfree(a5xx_state->hlsqregs);

		msm_gem_kernel_put(dumper.bo, gpu->aspace);

		msm_gem_kernel_put(dumper.bo, gpu->vm);

		return;

	}
@@ -1565,7 +1565,7 @@ static void a5xx_gpu_state_get_hlsq_regs(struct msm_gpu *gpu, 
	memcpy(a5xx_state->hlsqregs, dumper.ptr + (256 * SZ_1K),

		count * sizeof(u32));



	msm_gem_kernel_put(dumper.bo, gpu->aspace);

	msm_gem_kernel_put(dumper.bo, gpu->vm);

}



static struct msm_gpu_state *a5xx_gpu_state_get(struct msm_gpu *gpu)
@@ -1713,7 +1713,7 @@ static const struct adreno_gpu_funcs funcs = { 
		.gpu_busy = a5xx_gpu_busy,

		.gpu_state_get = a5xx_gpu_state_get,

		.gpu_state_put = a5xx_gpu_state_put,

		.create_address_space = adreno_create_address_space,

		.create_vm = adreno_create_vm,

		.get_rptr = a5xx_get_rptr,

	},

	.get_timestamp = a5xx_get_timestamp,
@@ -1786,8 +1786,8 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) 
		return ERR_PTR(ret);

	}



	if (gpu->aspace)

		msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu, a5xx_fault_handler);

	if (gpu->vm)

		msm_mmu_set_fault_handler(gpu->vm->mmu, gpu, a5xx_fault_handler);



	/* Set up the preemption specific bits and pieces for each ringbuffer */

	a5xx_preempt_init(gpu);