Commit 05bd7e74 authored Dec 01, 2020 by Hawking Zhang Committed by Alex Deucher Dec 23, 2020

drm/amdgpu: correct ih_chicken programming for vega10/vega20 ih blocks



IH_CHICKEN.MC_SPACE_FBPA_ENABLE field is only
valid when IH_RB_CNTL.MC_SPACE is programed to 0x3,
frame buffer physical address. For both bus address
and gpu virtual address, don't program MC_SPACE_FBPA_ENABLE
field

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent 580a6d2f

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

+0 −3

Original line number	Diff line number	Diff line
		@@ -281,9 +281,6 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
		if (adev->irq.ih.use_bus_addr) {
		ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,
		MC_SPACE_GPA_ENABLE, 1);
		} else {
		ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,
		MC_SPACE_FBPA_ENABLE, 1);
		}
		WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken);
		}

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

+0 −3

Original line number	Diff line number	Diff line
		@@ -312,9 +312,6 @@ static int vega20_ih_irq_init(struct amdgpu_device *adev)
		if (adev->irq.ih.use_bus_addr) {
		ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,
		MC_SPACE_GPA_ENABLE, 1);
		} else {
		ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,
		MC_SPACE_FBPA_ENABLE, 1);
		}
		WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken);
		}