Commit 0608235a authored by Linus Walleij's avatar Linus Walleij
Browse files

Merge tag 'renesas-pinctrl-for-v6.11-tag2-v2' of... 

Merge tag 'renesas-pinctrl-for-v6.11-tag2-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers

 into devel

Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parents 0cd9f140 71062e52

drivers/pinctrl/renesas/pfc-r8a779g0.c

+462 −368

File changed.

Preview size limit exceeded, changes collapsed.

drivers/pinctrl/renesas/pfc-r8a779h0.c

+61 −21
Original line number Diff line number Diff line
@@ -1236,6 +1236,30 @@ static const unsigned int avb0_mdio_pins[] = { 
static const unsigned int avb0_mdio_mux[] = {

	AVB0_MDC_MARK, AVB0_MDIO_MARK,

};

static const unsigned int avb0_mii_pins[] = {

	/*

	 * AVB0_MII_TD0, AVB0_MII_TD1, AVB0_MII_TD2,

	 * AVB0_MII_TD3, AVB0_MII_RD0, AVB0_MII_RD1,

	 * AVB0_MII_RD2, AVB0_MII_RD3, AVB0_MII_TXC,

	 * AVB0_MII_TX_EN, AVB0_MII_TX_ER, AVB0_MII_RXC,

	 * AVB0_MII_RX_DV, AVB0_MII_RX_ER, AVB0_MII_CRS,

	 * AVB0_MII_COL

	 */

	RCAR_GP_PIN(7, 11), RCAR_GP_PIN(7,  7), RCAR_GP_PIN(7,  6),

	RCAR_GP_PIN(7,  3), RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),

	RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7,  8), RCAR_GP_PIN(7, 15),

	RCAR_GP_PIN(7, 16), RCAR_GP_PIN(7,  4), RCAR_GP_PIN(7, 19),

	RCAR_GP_PIN(7, 20), RCAR_GP_PIN(7,  2), RCAR_GP_PIN(7,  1),

	RCAR_GP_PIN(7,  0),

};

static const unsigned int avb0_mii_mux[] = {

	AVB0_MII_TD0_MARK, AVB0_MII_TD1_MARK, AVB0_MII_TD2_MARK,

	AVB0_MII_TD3_MARK, AVB0_MII_RD0_MARK, AVB0_MII_RD1_MARK,

	AVB0_MII_RD2_MARK, AVB0_MII_RD3_MARK, AVB0_MII_TXC_MARK,

	AVB0_MII_TX_EN_MARK, AVB0_MII_TX_ER_MARK, AVB0_MII_RXC_MARK,

	AVB0_MII_RX_DV_MARK, AVB0_MII_RX_ER_MARK, AVB0_MII_CRS_MARK,

	AVB0_MII_COL_MARK,

};

static const unsigned int avb0_rgmii_pins[] = {

	/*

	 * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
@@ -1314,6 +1338,30 @@ static const unsigned int avb1_mdio_pins[] = { 
static const unsigned int avb1_mdio_mux[] = {

	AVB1_MDC_MARK, AVB1_MDIO_MARK,

};

static const unsigned int avb1_mii_pins[] = {

	/*

	 * AVB1_MII_TD0, AVB1_MII_TD1, AVB1_MII_TD2,

	 * AVB1_MII_TD3, AVB1_MII_RD0, AVB1_MII_RD1,

	 * AVB1_MII_RD2, AVB1_MII_RD3, AVB1_MII_TXC,

	 * AVB1_MII_TX_EN, AVB1_MII_TX_ER, AVB1_MII_RXC,

	 * AVB1_MII_RX_DV, AVB1_MII_RX_ER, AVB1_MII_CRS,

	 * AVB1_MII_COL

	 */

	RCAR_GP_PIN(6, 13), RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 16),

	RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14),

	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 19), RCAR_GP_PIN(6,  6),

	RCAR_GP_PIN(6,  7), RCAR_GP_PIN(6,  4), RCAR_GP_PIN(6,  8),

	RCAR_GP_PIN(6,  9), RCAR_GP_PIN(6,  5), RCAR_GP_PIN(6, 11),

	RCAR_GP_PIN(6, 10),

};

static const unsigned int avb1_mii_mux[] = {

	AVB1_MII_TD0_MARK, AVB1_MII_TD1_MARK, AVB1_MII_TD2_MARK,

	AVB1_MII_TD3_MARK, AVB1_MII_RD0_MARK, AVB1_MII_RD1_MARK,

	AVB1_MII_RD2_MARK, AVB1_MII_RD3_MARK, AVB1_MII_TXC_MARK,

	AVB1_MII_TX_EN_MARK, AVB1_MII_TX_ER_MARK, AVB1_MII_RXC_MARK,

	AVB1_MII_RX_DV_MARK, AVB1_MII_RX_ER_MARK, AVB1_MII_CRS_MARK,

	AVB1_MII_COL_MARK,

};

static const unsigned int avb1_rgmii_pins[] = {

	/*

	 * AVB1_TX_CTL, AVB1_TXC, AVB1_TD0, AVB1_TD1, AVB1_TD2, AVB1_TD3,
@@ -1509,7 +1557,7 @@ static const unsigned int hscif0_ctrl_mux[] = { 
	HRTS0_N_MARK, HCTS0_N_MARK,

};



/* - HSCIF1_A ----------------------------------------------------------------- */

/* - HSCIF1 ------------------------------------------------------------------- */

static const unsigned int hscif1_data_a_pins[] = {

	/* HRX1_A, HTX1_A */

	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
@@ -1532,7 +1580,6 @@ static const unsigned int hscif1_ctrl_a_mux[] = { 
	HRTS1_N_A_MARK, HCTS1_N_A_MARK,

};



/* - HSCIF1_B ---------------------------------------------------------------- */

static const unsigned int hscif1_data_b_pins[] = {

	/* HRX1_B, HTX1_B */

	RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
@@ -1578,7 +1625,7 @@ static const unsigned int hscif2_ctrl_mux[] = { 
	HRTS2_N_MARK, HCTS2_N_MARK,

};



/* - HSCIF3_A ----------------------------------------------------------------- */

/* - HSCIF3 ------------------------------------------------------------------- */

static const unsigned int hscif3_data_a_pins[] = {

	/* HRX3_A, HTX3_A */

	RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 28),
@@ -1601,7 +1648,6 @@ static const unsigned int hscif3_ctrl_a_mux[] = { 
	HRTS3_N_A_MARK, HCTS3_N_A_MARK,

};



/* - HSCIF3_B ----------------------------------------------------------------- */

static const unsigned int hscif3_data_b_pins[] = {

	/* HRX3_B, HTX3_B */

	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0),
@@ -2061,7 +2107,7 @@ static const unsigned int pcie0_clkreq_n_mux[] = { 
	PCIE0_CLKREQ_N_MARK,

};



/* - PWM0_A ------------------------------------------------------------------- */

/* - PWM0 --------------------------------------------------------------------- */

static const unsigned int pwm0_a_pins[] = {

	/* PWM0_A */

	RCAR_GP_PIN(1, 15),
@@ -2070,7 +2116,6 @@ static const unsigned int pwm0_a_mux[] = { 
	PWM0_A_MARK,

};



/* - PWM0_B ------------------------------------------------------------------- */

static const unsigned int pwm0_b_pins[] = {

	/* PWM0_B */

	RCAR_GP_PIN(1, 14),
@@ -2079,7 +2124,7 @@ static const unsigned int pwm0_b_mux[] = { 
	PWM0_B_MARK,

};



/* - PWM1_A ------------------------------------------------------------------- */

/* - PWM1 --------------------------------------------------------------------- */

static const unsigned int pwm1_a_pins[] = {

	/* PWM1_A */

	RCAR_GP_PIN(3, 13),
@@ -2088,7 +2133,6 @@ static const unsigned int pwm1_a_mux[] = { 
	PWM1_A_MARK,

};



/* - PWM1_B ------------------------------------------------------------------- */

static const unsigned int pwm1_b_pins[] = {

	/* PWM1_B */

	RCAR_GP_PIN(2, 13),
@@ -2097,7 +2141,6 @@ static const unsigned int pwm1_b_mux[] = { 
	PWM1_B_MARK,

};



/* - PWM1_C ------------------------------------------------------------------- */

static const unsigned int pwm1_c_pins[] = {

	/* PWM1_C */

	RCAR_GP_PIN(2, 17),
@@ -2106,7 +2149,7 @@ static const unsigned int pwm1_c_mux[] = { 
	PWM1_C_MARK,

};



/* - PWM2_A ------------------------------------------------------------------- */

/* - PWM2 --------------------------------------------------------------------- */

static const unsigned int pwm2_a_pins[] = {

	/* PWM2_A */

	RCAR_GP_PIN(3, 14),
@@ -2115,7 +2158,6 @@ static const unsigned int pwm2_a_mux[] = { 
	PWM2_A_MARK,

};



/* - PWM2_B ------------------------------------------------------------------- */

static const unsigned int pwm2_b_pins[] = {

	/* PWM2_B */

	RCAR_GP_PIN(2, 14),
@@ -2124,7 +2166,6 @@ static const unsigned int pwm2_b_mux[] = { 
	PWM2_B_MARK,

};



/* - PWM2_C ------------------------------------------------------------------- */

static const unsigned int pwm2_c_pins[] = {

	/* PWM2_C */

	RCAR_GP_PIN(2, 19),
@@ -2133,7 +2174,7 @@ static const unsigned int pwm2_c_mux[] = { 
	PWM2_C_MARK,

};



/* - PWM3_A ------------------------------------------------------------------- */

/* - PWM3 --------------------------------------------------------------------- */

static const unsigned int pwm3_a_pins[] = {

	/* PWM3_A */

	RCAR_GP_PIN(4, 14),
@@ -2142,7 +2183,6 @@ static const unsigned int pwm3_a_mux[] = { 
	PWM3_A_MARK,

};



/* - PWM3_B ------------------------------------------------------------------- */

static const unsigned int pwm3_b_pins[] = {

	/* PWM3_B */

	RCAR_GP_PIN(2, 15),
@@ -2151,7 +2191,6 @@ static const unsigned int pwm3_b_mux[] = { 
	PWM3_B_MARK,

};



/* - PWM3_C ------------------------------------------------------------------- */

static const unsigned int pwm3_c_pins[] = {

	/* PWM3_C */

	RCAR_GP_PIN(1, 22),
@@ -2228,7 +2267,7 @@ static const unsigned int scif0_ctrl_mux[] = { 
	RTS0_N_MARK, CTS0_N_MARK,

};



/* - SCIF1_A ------------------------------------------------------------------ */

/* - SCIF1 -------------------------------------------------------------------- */

static const unsigned int scif1_data_a_pins[] = {

	/* RX1_A, TX1_A */

	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
@@ -2251,7 +2290,6 @@ static const unsigned int scif1_ctrl_a_mux[] = { 
	RTS1_N_A_MARK, CTS1_N_A_MARK,

};



/* - SCIF1_B ------------------------------------------------------------------ */

static const unsigned int scif1_data_b_pins[] = {

	/* RX1_B, TX1_B */

	RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
@@ -2274,7 +2312,7 @@ static const unsigned int scif1_ctrl_b_mux[] = { 
	RTS1_N_B_MARK, CTS1_N_B_MARK,

};



/* - SCIF3_A ------------------------------------------------------------------ */

/* - SCIF3 -------------------------------------------------------------------- */

static const unsigned int scif3_data_a_pins[] = {

	/* RX3_A, TX3_A */

	RCAR_GP_PIN(1, 27), RCAR_GP_PIN(1, 28),
@@ -2297,7 +2335,6 @@ static const unsigned int scif3_ctrl_a_mux[] = { 
	RTS3_N_A_MARK, CTS3_N_A_MARK,

};



/* - SCIF3_B ------------------------------------------------------------------ */

static const unsigned int scif3_data_b_pins[] = {

	/* RX3_B, TX3_B */

	RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
@@ -2376,7 +2413,7 @@ static const unsigned int ssi_ctrl_mux[] = { 
	SSI_SCK_MARK, SSI_WS_MARK,

};



/* - TPU_A ------------------------------------------------------------------- */

/* - TPU --------------------------------------------------------------------- */

static const unsigned int tpu_to0_a_pins[] = {

	/* TPU0TO0_A */

	RCAR_GP_PIN(2, 8),
@@ -2406,7 +2443,6 @@ static const unsigned int tpu_to3_a_mux[] = { 
	TPU0TO3_A_MARK,

};



/* - TPU_B ------------------------------------------------------------------- */

static const unsigned int tpu_to0_b_pins[] = {

	/* TPU0TO0_B */

	RCAR_GP_PIN(1, 25),
@@ -2444,6 +2480,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { 
	SH_PFC_PIN_GROUP(avb0_magic),

	SH_PFC_PIN_GROUP(avb0_phy_int),

	SH_PFC_PIN_GROUP(avb0_mdio),

	SH_PFC_PIN_GROUP(avb0_mii),

	SH_PFC_PIN_GROUP(avb0_rgmii),

	SH_PFC_PIN_GROUP(avb0_txcrefclk),

	SH_PFC_PIN_GROUP(avb0_avtp_pps),
@@ -2454,6 +2491,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { 
	SH_PFC_PIN_GROUP(avb1_magic),

	SH_PFC_PIN_GROUP(avb1_phy_int),

	SH_PFC_PIN_GROUP(avb1_mdio),

	SH_PFC_PIN_GROUP(avb1_mii),

	SH_PFC_PIN_GROUP(avb1_rgmii),

	SH_PFC_PIN_GROUP(avb1_txcrefclk),

	SH_PFC_PIN_GROUP(avb1_avtp_pps),
@@ -2628,6 +2666,7 @@ static const char * const avb0_groups[] = { 
	"avb0_magic",

	"avb0_phy_int",

	"avb0_mdio",

	"avb0_mii",

	"avb0_rgmii",

	"avb0_txcrefclk",

	"avb0_avtp_pps",
@@ -2640,6 +2679,7 @@ static const char * const avb1_groups[] = { 
	"avb1_magic",

	"avb1_phy_int",

	"avb1_mdio",

	"avb1_mii",

	"avb1_rgmii",

	"avb1_txcrefclk",

	"avb1_avtp_pps",

drivers/pinctrl/renesas/pfc-sh73a0.c

+2 −2
Original line number Diff line number Diff line
@@ -4024,7 +4024,7 @@ static const struct pinmux_irq pinmux_irqs[] = { 


static void sh73a0_vccq_mc0_endisable(struct regulator_dev *reg, bool enable)

{

	struct sh_pfc *pfc = reg->reg_data;

	struct sh_pfc *pfc = rdev_get_drvdata(reg);

	void __iomem *addr = pfc->windows[1].virt + 4;

	unsigned long flags;

	u32 value;
@@ -4057,7 +4057,7 @@ static int sh73a0_vccq_mc0_disable(struct regulator_dev *reg) 


static int sh73a0_vccq_mc0_is_enabled(struct regulator_dev *reg)

{

	struct sh_pfc *pfc = reg->reg_data;

	struct sh_pfc *pfc = rdev_get_drvdata(reg);

	void __iomem *addr = pfc->windows[1].virt + 4;

	unsigned long flags;

	u32 value;

drivers/pinctrl/renesas/pinctrl-rzg2l.c

+32 −27
Original line number Diff line number Diff line
@@ -57,12 +57,14 @@ 
#define PIN_CFG_IOLH_C			BIT(13)

#define PIN_CFG_SOFT_PS			BIT(14)

#define PIN_CFG_OEN			BIT(15)

#define PIN_CFG_VARIABLE		BIT(16)

#define PIN_CFG_NOGPIO_INT		BIT(17)

#define PIN_CFG_NOD			BIT(18)	/* N-ch Open Drain */

#define PIN_CFG_SMT			BIT(19)	/* Schmitt-trigger input control */

#define PIN_CFG_ELC			BIT(20)

#define PIN_CFG_IOLH_RZV2H		BIT(21)

#define PIN_CFG_NOGPIO_INT		BIT(16)

#define PIN_CFG_NOD			BIT(17)	/* N-ch Open Drain */

#define PIN_CFG_SMT			BIT(18)	/* Schmitt-trigger input control */

#define PIN_CFG_ELC			BIT(19)

#define PIN_CFG_IOLH_RZV2H		BIT(20)



#define RZG2L_SINGLE_PIN		BIT_ULL(63)	/* Dedicated pin */

#define RZG2L_VARIABLE_CFG		BIT_ULL(62)	/* Variable cfg for port pins */



#define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \

					(PIN_CFG_IOLH_##group | \
@@ -87,9 +89,9 @@ 
					 PIN_CFG_FILNUM | \

					 PIN_CFG_FILCLKSEL)



#define PIN_CFG_PIN_MAP_MASK		GENMASK_ULL(62, 55)

#define PIN_CFG_PIN_REG_MASK		GENMASK_ULL(54, 47)

#define PIN_CFG_MASK			GENMASK_ULL(46, 0)

#define PIN_CFG_PIN_MAP_MASK		GENMASK_ULL(61, 54)

#define PIN_CFG_PIN_REG_MASK		GENMASK_ULL(53, 46)

#define PIN_CFG_MASK			GENMASK_ULL(31, 0)



/*

 * m indicates the bitmap of supported pins, a is the register index
@@ -98,22 +100,25 @@ 
#define RZG2L_GPIO_PORT_SPARSE_PACK(m, a, f)	(FIELD_PREP_CONST(PIN_CFG_PIN_MAP_MASK, (m)) | \

						 FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a)) | \

						 FIELD_PREP_CONST(PIN_CFG_MASK, (f)))

#define RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(m, a)	\

						(RZG2L_VARIABLE_CFG | \

						 RZG2L_GPIO_PORT_SPARSE_PACK(m, a, 0))



/*

 * n indicates number of pins in the port, a is the register index

 * and f is pin configuration capabilities supported.

 */

#define RZG2L_GPIO_PORT_PACK(n, a, f)	RZG2L_GPIO_PORT_SPARSE_PACK((1ULL << (n)) - 1, (a), (f))

#define RZG2L_GPIO_PORT_PACK_VARIABLE(n, a)	(RZG2L_VARIABLE_CFG | \

						 RZG2L_GPIO_PORT_PACK(n, a, 0))



/*

 * BIT(63) indicates dedicated pin, p is the register index while

 * referencing to SR/IEN/IOLH/FILxx registers, b is the register bits

 * (b * 8) and f is the pin configuration capabilities supported.

 */

#define RZG2L_SINGLE_PIN		BIT_ULL(63)

#define RZG2L_SINGLE_PIN_INDEX_MASK	GENMASK_ULL(62, 56)

#define RZG2L_SINGLE_PIN_BITS_MASK	GENMASK_ULL(55, 53)



/*

 * p is the register index while referencing to SR/IEN/IOLH/FILxx

 * registers, b is the register bits (b * 8) and f is the pin

 * configuration capabilities supported.

 */

#define RZG2L_SINGLE_PIN_PACK(p, b, f)	(RZG2L_SINGLE_PIN | \

					 FIELD_PREP_CONST(RZG2L_SINGLE_PIN_INDEX_MASK, (p)) | \

					 FIELD_PREP_CONST(RZG2L_SINGLE_PIN_BITS_MASK, (b)) | \
@@ -371,7 +376,7 @@ static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl, 


		if (FIELD_GET(VARIABLE_PIN_CFG_PORT_MASK, cfg) == port &&

		    FIELD_GET(VARIABLE_PIN_CFG_PIN_MASK, cfg) == pin)

			return (pincfg & ~PIN_CFG_VARIABLE) | FIELD_GET(PIN_CFG_MASK, cfg);

			return (pincfg & ~RZG2L_VARIABLE_CFG) | FIELD_GET(PIN_CFG_MASK, cfg);

	}



	return 0;
@@ -1187,7 +1192,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, 
	u64 *pin_data = pin->drv_data;

	unsigned int arg = 0;

	u32 off;

	u64 cfg;

	u32 cfg;

	int ret;

	u8 bit;
@@ -1322,7 +1327,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, 
	u64 *pin_data = pin->drv_data;

	unsigned int i, arg, index;

	u32 off, param;

	u64 cfg;

	u32 cfg;

	int ret;

	u8 bit;
@@ -1835,13 +1840,13 @@ static const u64 r9a07g043_gpio_configs[] = { 
	RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x06, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |

				    PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |

				    PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),			/* P19 */

	RZG2L_GPIO_PORT_PACK(8, 0x07, PIN_CFG_VARIABLE),				/* P20 */

	RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x07),						/* P20 */

	RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x08, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |

				    PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),			/* P21 */

	RZG2L_GPIO_PORT_PACK(4, 0x09, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |

			     PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),				/* P22 */

	RZG2L_GPIO_PORT_SPARSE_PACK(0x3e, 0x0a, PIN_CFG_VARIABLE),			/* P23 */

	RZG2L_GPIO_PORT_PACK(6, 0x0b, PIN_CFG_VARIABLE),				/* P24 */

	RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(0x3e, 0x0a),				/* P23 */

	RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x0b),						/* P24 */

	RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x0c, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_FILONOFF |

				    PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |

				    PIN_CFG_NOGPIO_INT),				/* P25 */
@@ -1913,7 +1918,7 @@ static const u64 r9a09g057_gpio_configs[] = { 
				      PIN_CFG_ELC),		/* P8 */

	RZG2L_GPIO_PORT_PACK(8, 0x29, RZV2H_MPXED_PIN_FUNCS),	/* P9 */

	RZG2L_GPIO_PORT_PACK(8, 0x2a, RZV2H_MPXED_PIN_FUNCS),	/* PA */

	RZG2L_GPIO_PORT_PACK(6, 0x2b, PIN_CFG_VARIABLE),	/* PB */

	RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x2b),			/* PB */

};



static const struct {
@@ -2637,7 +2642,7 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) 
		if (i && !(i % RZG2L_PINS_PER_PORT))

			j++;

		pin_data[i] = pctrl->data->port_pin_configs[j];

		if (pin_data[i] & PIN_CFG_VARIABLE)

		if (pin_data[i] & RZG2L_VARIABLE_CFG)

			pin_data[i] = rzg2l_pinctrl_get_variable_pin_cfg(pctrl,

									 pin_data[i],

									 j,
@@ -2755,9 +2760,9 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen 


	for (u32 port = 0; port < nports; port++) {

		bool has_iolh, has_ien;

		u64 cfg, caps;

		u32 off, caps;

		u8 pincnt;

		u32 off;

		u64 cfg;



		cfg = pctrl->data->port_pin_configs[port];

		off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg);
@@ -2801,7 +2806,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen 
static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, bool suspend)

{

	struct rzg2l_pinctrl_reg_cache *cache = pctrl->dedicated_cache;

	u64 caps;

	u32 caps;

	u32 i;



	/*