Commit 061093d7 authored by José Roberto de Souza's avatar José Roberto de Souza
Browse files

drm/i915/display/adl_p: Implement Wa_22012278275 



The PSR2_CTL io buffer wake and fast wake values do not match
expected in pre production hardware, so here adding a table that
matches with HW to program it with values that HW expect.

Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Reviewed-by: default avatarGwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210616203158.118111-2-jose.souza@intel.com
parent 0e20b769

drivers/gpu/drm/i915/display/intel_psr.c

+28 −1
Original line number Diff line number Diff line
@@ -542,7 +542,34 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) 
	val |= EDP_PSR2_FRAME_BEFORE_SU(intel_dp->psr.sink_sync_latency + 1);

	val |= intel_psr2_get_tp_time(intel_dp);



	if (DISPLAY_VER(dev_priv) >= 12) {

	/* Wa_22012278275:adlp */

	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_D1)) {

		static const u8 map[] = {

			2, /* 5 lines */

			1, /* 6 lines */

			0, /* 7 lines */

			3, /* 8 lines */

			6, /* 9 lines */

			5, /* 10 lines */

			4, /* 11 lines */

			7, /* 12 lines */

		};

		/*

		 * Still using the default IO_BUFFER_WAKE and FAST_WAKE, see

		 * comments bellow for more information

		 */

		u32 tmp, lines = 7;



		val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2;



		tmp = map[lines - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES];

		tmp = tmp << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT;

		val |= tmp;



		tmp = map[lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES];

		tmp = tmp << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT;

		val |= tmp;

	} else if (DISPLAY_VER(dev_priv) >= 12) {

		/*

		 * TODO: 7 lines of IO_BUFFER_WAKE and FAST_WAKE are default

		 * values from BSpec. In order to setting an optimal power

drivers/gpu/drm/i915/i915_reg.h

+4 −2
Original line number Diff line number Diff line
@@ -4584,13 +4584,15 @@ enum { 
#define   EDP_PSR2_IO_BUFFER_WAKE(lines)	((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) << 13)

#define   EDP_PSR2_IO_BUFFER_WAKE_MASK		(3 << 13)

#define   TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES	5

#define   TGL_EDP_PSR2_IO_BUFFER_WAKE(lines)	(((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << 13)

#define   TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT	13

#define   TGL_EDP_PSR2_IO_BUFFER_WAKE(lines)	(((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT)

#define   TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK	(7 << 13)

#define   EDP_PSR2_FAST_WAKE_MAX_LINES		8

#define   EDP_PSR2_FAST_WAKE(lines)		((EDP_PSR2_FAST_WAKE_MAX_LINES - (lines)) << 11)

#define   EDP_PSR2_FAST_WAKE_MASK		(3 << 11)

#define   TGL_EDP_PSR2_FAST_WAKE_MIN_LINES	5

#define   TGL_EDP_PSR2_FAST_WAKE(lines)		(((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << 10)

#define   TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT	10

#define   TGL_EDP_PSR2_FAST_WAKE(lines)		(((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT)

#define   TGL_EDP_PSR2_FAST_WAKE_MASK		(7 << 10)

#define   EDP_PSR2_TP2_TIME_500us		(0 << 8)

#define   EDP_PSR2_TP2_TIME_100us		(1 << 8)