Commit 0635d554 authored by Uma Shankar's avatar Uma Shankar
Browse files

drm/i915: Extract display registers from i915_reg.h to display 



There are certain register definitions which are defined in i915_reg.h
which are exclusively needed by display. Move the same to display
headers to remove i915_reg.h includes from display. This is a step
towards making display independent of i915.

intel_clock_gating.c can include display header directly, since its
usage is planned to be re-factored and will be moved within display.

v3: Updated subject and commit message (Jani)

v2: Drop common header in include and use display_regs.h (Jani)

Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarUma Shankar <uma.shankar@intel.com>
Link: https://patch.msgid.link/20260205094341.1882816-2-uma.shankar@intel.com
parent c0a27a0c

drivers/gpu/drm/i915/display/intel_display_regs.h

+10 −0
Original line number Diff line number Diff line
@@ -2021,6 +2021,16 @@ 
#define  TRANS_BPC_6			REG_FIELD_PREP(TRANS_BPC_MASK, 2)

#define  TRANS_BPC_12			REG_FIELD_PREP(TRANS_BPC_MASK, 3)



#define _TRANSA_CHICKEN2	0xf0064

#define _TRANSB_CHICKEN2	0xf1064

#define TRANS_CHICKEN2(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)

#define   TRANS_CHICKEN2_TIMING_OVERRIDE		REG_BIT(31)

#define   TRANS_CHICKEN2_FDI_POLARITY_REVERSED		REG_BIT(29)

#define   TRANS_CHICKEN2_FRAME_START_DELAY_MASK		REG_GENMASK(28, 27)

#define   TRANS_CHICKEN2_FRAME_START_DELAY(x)		REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */

#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER	REG_BIT(26)

#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH	REG_BIT(25)



#define PCH_DP_B		_MMIO(0xe4100)

#define PCH_DP_C		_MMIO(0xe4200)

#define PCH_DP_D		_MMIO(0xe4300)

drivers/gpu/drm/i915/display/intel_pch_display.c

+0 −1
Original line number Diff line number Diff line
@@ -6,7 +6,6 @@ 
#include <drm/drm_print.h>



#include "g4x_dp.h"

#include "i915_reg.h"

#include "intel_crt.h"

#include "intel_crt_regs.h"

#include "intel_de.h"

drivers/gpu/drm/i915/i915_reg.h

+0 −10
Original line number Diff line number Diff line
@@ -1023,16 +1023,6 @@ 
#define   TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	REG_BIT(10)

#define   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	REG_BIT(4)



#define _TRANSA_CHICKEN2	 0xf0064

#define _TRANSB_CHICKEN2	 0xf1064

#define TRANS_CHICKEN2(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)

#define   TRANS_CHICKEN2_TIMING_OVERRIDE		REG_BIT(31)

#define   TRANS_CHICKEN2_FDI_POLARITY_REVERSED		REG_BIT(29)

#define   TRANS_CHICKEN2_FRAME_START_DELAY_MASK		REG_GENMASK(28, 27)

#define   TRANS_CHICKEN2_FRAME_START_DELAY(x)		REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */

#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER	REG_BIT(26)

#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH	REG_BIT(25)



#define SOUTH_CHICKEN1		_MMIO(0xc2000)

#define  FDIA_PHASE_SYNC_SHIFT_OVR	19

#define  FDIA_PHASE_SYNC_SHIFT_EN	18

drivers/gpu/drm/i915/intel_clock_gating.c

+1 −1
Original line number Diff line number Diff line
@@ -30,7 +30,7 @@ 
#include "display/i9xx_plane_regs.h"

#include "display/intel_display.h"

#include "display/intel_display_core.h"



#include "display/intel_display_regs.h"

#include "gt/intel_engine_regs.h"

#include "gt/intel_gt.h"

#include "gt/intel_gt_mcr.h"