Commit 0638dec0 authored by Herbert Valerio Riedel's avatar Herbert Valerio Riedel Committed by Jeff Garzik
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[PATCH] net: au1000_eth: PHY framework conversion 



convert au1000_eth driver to use PHY framework and garbage collected
functions and identifiers that became unused/obsolete in the process

Signed-off-by: default avatarHerbert Valerio Riedel <hvr@gnu.org>
Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
parent 96e672c7

drivers/net/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -447,6 +447,7 @@ config MIPS_GT96100ETH 
config MIPS_AU1X00_ENET

	bool "MIPS AU1000 Ethernet support"

	depends on NET_ETHERNET && SOC_AU1X00

	select PHYLIB

	select CRC32

	help

	  If you have an Alchemy Semi AU1X00 based system

drivers/net/au1000_eth.c

+368 −1234

File changed.

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drivers/net/au1000_eth.h

+9 −125
Original line number Diff line number Diff line
@@ -40,120 +40,6 @@ 


#define MULTICAST_FILTER_LIMIT 64



/* FIXME 

 * The PHY defines should be in a separate file.

 */



/* MII register offsets */

#define	MII_CONTROL 0x0000

#define MII_STATUS  0x0001

#define MII_PHY_ID0 0x0002

#define	MII_PHY_ID1 0x0003

#define MII_ANADV   0x0004

#define MII_ANLPAR  0x0005

#define MII_AEXP    0x0006

#define MII_ANEXT   0x0007

#define MII_LSI_PHY_CONFIG 0x0011

/* Status register */

#define MII_LSI_PHY_STAT   0x0012

#define MII_AMD_PHY_STAT   MII_LSI_PHY_STAT

#define MII_INTEL_PHY_STAT 0x0011



#define MII_AUX_CNTRL  0x0018

/* mii registers specific to AMD 79C901 */

#define	MII_STATUS_SUMMARY = 0x0018



/* MII Control register bit definitions. */

#define	MII_CNTL_FDX      0x0100

#define MII_CNTL_RST_AUTO 0x0200

#define	MII_CNTL_ISOLATE  0x0400

#define MII_CNTL_PWRDWN   0x0800

#define	MII_CNTL_AUTO     0x1000

#define MII_CNTL_F100     0x2000

#define	MII_CNTL_LPBK     0x4000

#define MII_CNTL_RESET    0x8000



/* MII Status register bit  */

#define	MII_STAT_EXT        0x0001 

#define MII_STAT_JAB        0x0002

#define	MII_STAT_LINK       0x0004

#define MII_STAT_CAN_AUTO   0x0008

#define	MII_STAT_FAULT      0x0010 

#define MII_STAT_AUTO_DONE  0x0020

#define	MII_STAT_CAN_T      0x0800

#define MII_STAT_CAN_T_FDX  0x1000

#define	MII_STAT_CAN_TX     0x2000 

#define MII_STAT_CAN_TX_FDX 0x4000

#define	MII_STAT_CAN_T4     0x8000





#define		MII_ID1_OUI_LO		0xFC00	/* low bits of OUI mask */

#define		MII_ID1_MODEL		0x03F0	/* model number */

#define		MII_ID1_REV		0x000F	/* model number */



/* MII NWAY Register Bits ...

   valid for the ANAR (Auto-Negotiation Advertisement) and

   ANLPAR (Auto-Negotiation Link Partner) registers */

#define	MII_NWAY_NODE_SEL 0x001f

#define MII_NWAY_CSMA_CD  0x0001

#define	MII_NWAY_T	  0x0020

#define MII_NWAY_T_FDX    0x0040

#define	MII_NWAY_TX       0x0080

#define MII_NWAY_TX_FDX   0x0100

#define	MII_NWAY_T4       0x0200 

#define MII_NWAY_PAUSE    0x0400 

#define	MII_NWAY_RF       0x2000 /* Remote Fault */

#define MII_NWAY_ACK      0x4000 /* Remote Acknowledge */

#define	MII_NWAY_NP       0x8000 /* Next Page (Enable) */



/* mii stsout register bits */

#define	MII_STSOUT_LINK_FAIL 0x4000

#define	MII_STSOUT_SPD       0x0080

#define MII_STSOUT_DPLX      0x0040



/* mii stsics register bits */

#define	MII_STSICS_SPD       0x8000

#define MII_STSICS_DPLX      0x4000

#define	MII_STSICS_LINKSTS   0x0001



/* mii stssum register bits */

#define	MII_STSSUM_LINK  0x0008

#define MII_STSSUM_DPLX  0x0004

#define	MII_STSSUM_AUTO  0x0002

#define MII_STSSUM_SPD   0x0001



/* lsi phy status register */

#define MII_LSI_PHY_STAT_FDX	0x0040

#define MII_LSI_PHY_STAT_SPD	0x0080



/* amd phy status register */

#define MII_AMD_PHY_STAT_FDX	0x0800

#define MII_AMD_PHY_STAT_SPD	0x0400



/* intel phy status register */

#define MII_INTEL_PHY_STAT_FDX	0x0200

#define MII_INTEL_PHY_STAT_SPD	0x4000



/* Auxilliary Control/Status Register */

#define MII_AUX_FDX      0x0001

#define MII_AUX_100      0x0002

#define MII_AUX_F100     0x0004

#define MII_AUX_ANEG     0x0008



typedef struct mii_phy {

	struct mii_phy * next;

	struct mii_chip_info * chip_info;

	u16 status;

	u32 *mii_control_reg;

	u32 *mii_data_reg;

} mii_phy_t;



struct phy_ops {

	int (*phy_init) (struct net_device *, int);

	int (*phy_reset) (struct net_device *, int);

	int (*phy_status) (struct net_device *, int, u16 *, u16 *);

};



/* 

 * Data Buffer Descriptor. Data buffers must be aligned on 32 byte 

 * boundary for both, receive and transmit.
@@ -200,7 +86,6 @@ typedef struct mac_reg { 




struct au1000_private {

	

	db_dest_t *pDBfree;

	db_dest_t db[NUM_RX_BUFFS+NUM_TX_BUFFS];

	volatile rx_dma_t *rx_dma_ring[NUM_RX_DMA];
@@ -213,8 +98,15 @@ struct au1000_private { 
	u32 tx_full;



	int mac_id;

	mii_phy_t *mii;

	struct phy_ops *phy_ops;



	int mac_enabled;       /* whether MAC is currently enabled and running (req. for mdio) */



	int old_link;          /* used by au1000_adjust_link */

	int old_speed;

	int old_duplex;



	struct phy_device *phy_dev;

	struct mii_bus mii_bus;

	

	/* These variables are just for quick access to certain regs addresses. */

	volatile mac_reg_t *mac;  /* mac registers                      */
@@ -223,14 +115,6 @@ struct au1000_private { 
	u32 vaddr;                /* virtual address of rx/tx buffers   */

	dma_addr_t dma_addr;      /* dma address of rx/tx buffers       */



	u8 *hash_table;

	u32 hash_mode;

	u32 intr_work_done; /* number of Rx and Tx pkts processed in the isr */

	int phy_addr;          /* phy address */

	u32 options;           /* User-settable misc. driver options. */

	u32 drv_flags;

	int want_autoneg;

	struct net_device_stats stats;

	struct timer_list timer;

	spinlock_t lock;       /* Serialise access to device */

};