Commit 0652a1c8 authored by Nicholas Kazlauskas's avatar Nicholas Kazlauskas Committed by Alex Deucher
Browse files

drm/amd/display: Add Z8 watermarks for DML2 bbox overrides 



[Why]
We can override SR watermarks but not Z8 ones.

[How]
Add new parameters for Z8 matching the SR ones and feed them into the
states.

These also weren't being applied to every state, so make sure that
we loop over and update all SOC states if given an override.

Reviewed-by: default avatarJun Lei <jun.lei@amd.com>
Acked-by: default avatarHamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8c4e9105

drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c

+32 −15
Original line number Diff line number Diff line
@@ -341,25 +341,42 @@ void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc, 
		break;

	}



	/* Override from passed values, mainly for debugging purposes, if available */

	/* Override from passed values, if available */

	for (i = 0; i < p->in_states->num_states; i++) {

		if (dml2->config.bbox_overrides.sr_exit_latency_us) {

		p->in_states->state_array[0].sr_exit_time_us = dml2->config.bbox_overrides.sr_exit_latency_us;

			p->in_states->state_array[i].sr_exit_time_us =

				dml2->config.bbox_overrides.sr_exit_latency_us;

		}



		if (dml2->config.bbox_overrides.sr_enter_plus_exit_latency_us) {

		p->in_states->state_array[0].sr_enter_plus_exit_time_us = dml2->config.bbox_overrides.sr_enter_plus_exit_latency_us;

			p->in_states->state_array[i].sr_enter_plus_exit_time_us =

				dml2->config.bbox_overrides.sr_enter_plus_exit_latency_us;

		}



		if (dml2->config.bbox_overrides.sr_exit_z8_time_us) {

			p->in_states->state_array[i].sr_exit_z8_time_us =

				dml2->config.bbox_overrides.sr_exit_z8_time_us;

		}



		if (dml2->config.bbox_overrides.sr_enter_plus_exit_z8_time_us) {

			p->in_states->state_array[i].sr_enter_plus_exit_z8_time_us =

				dml2->config.bbox_overrides.sr_enter_plus_exit_z8_time_us;

		}



		if (dml2->config.bbox_overrides.urgent_latency_us) {

		p->in_states->state_array[0].urgent_latency_pixel_data_only_us = dml2->config.bbox_overrides.urgent_latency_us;

			p->in_states->state_array[i].urgent_latency_pixel_data_only_us =

				dml2->config.bbox_overrides.urgent_latency_us;

		}



		if (dml2->config.bbox_overrides.dram_clock_change_latency_us) {

		p->in_states->state_array[0].dram_clock_change_latency_us = dml2->config.bbox_overrides.dram_clock_change_latency_us;

			p->in_states->state_array[i].dram_clock_change_latency_us =

				dml2->config.bbox_overrides.dram_clock_change_latency_us;

		}



		if (dml2->config.bbox_overrides.fclk_change_latency_us) {

		p->in_states->state_array[0].fclk_change_latency_us = dml2->config.bbox_overrides.fclk_change_latency_us;

			p->in_states->state_array[i].fclk_change_latency_us =

				dml2->config.bbox_overrides.fclk_change_latency_us;

		}

	}



	/* DCFCLK stas values are project specific */

drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h

+2 −0
Original line number Diff line number Diff line
@@ -139,6 +139,8 @@ struct dml2_soc_bbox_overrides { 
	double urgent_latency_us;

	double sr_exit_latency_us;

	double sr_enter_plus_exit_latency_us;

	double sr_exit_z8_time_us;

	double sr_enter_plus_exit_z8_time_us;

	double dram_clock_change_latency_us;

	double fclk_change_latency_us;

	unsigned int dram_num_chan;