Unverified Commit 06b010d3 authored by Andy Shevchenko's avatar Andy Shevchenko Committed by Mark Brown
Browse files

spi: microchip-core: Utilise temporary variable for struct device 



Add a temporary variable to keep a pointer to struct device.
Utilise it where it makes sense.

Signed-off-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: default avatarPrajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>
Link: https://patch.msgid.link/20251126075558.2035012-5-andriy.shevchenko@linux.intel.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 274b3458

drivers/spi/spi-microchip-core-spi.c

+21 −23
Original line number Diff line number Diff line
@@ -296,6 +296,7 @@ static int mchp_corespi_transfer_one(struct spi_controller *host, 
static int mchp_corespi_probe(struct platform_device *pdev)

{

	const char *protocol = "motorola";

	struct device *dev = &pdev->dev;

	struct spi_controller *host;

	struct mchp_corespi *spi;

	struct resource *res;
@@ -303,13 +304,13 @@ static int mchp_corespi_probe(struct platform_device *pdev) 
	bool assert_ssel;

	int ret = 0;



	host = devm_spi_alloc_host(&pdev->dev, sizeof(*spi));

	host = devm_spi_alloc_host(dev, sizeof(*spi));

	if (!host)

		return -ENOMEM;



	platform_set_drvdata(pdev, host);



	if (of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs))

	if (of_property_read_u32(dev->of_node, "num-cs", &num_cs))

		num_cs = MCHP_CORESPI_MAX_CS;



	/*
@@ -317,12 +318,12 @@ static int mchp_corespi_probe(struct platform_device *pdev) 
	 * CoreSPI can be configured for Motorola, TI or NSC.

	 * The current driver supports only Motorola mode.

	 */

	ret = of_property_read_string(pdev->dev.of_node, "microchip,protocol-configuration",

	ret = of_property_read_string(dev->of_node, "microchip,protocol-configuration",

				      &protocol);

	if (ret && ret != -EINVAL)

		return dev_err_probe(&pdev->dev, ret, "Error reading protocol-configuration\n");

		return dev_err_probe(dev, ret, "Error reading protocol-configuration\n");

	if (strcmp(protocol, "motorola") != 0)

		return dev_err_probe(&pdev->dev, -EINVAL,

		return dev_err_probe(dev, -EINVAL,

				     "CoreSPI: protocol '%s' not supported by this driver\n",

				      protocol);
@@ -330,11 +331,11 @@ static int mchp_corespi_probe(struct platform_device *pdev) 
	 * Motorola mode (0-3): CFG_MOT_MODE

	 * Mode is fixed in the IP configurator.

	 */

	ret = of_property_read_u32(pdev->dev.of_node, "microchip,motorola-mode", &mode);

	ret = of_property_read_u32(dev->of_node, "microchip,motorola-mode", &mode);

	if (ret)

		mode = MCHP_CORESPI_DEFAULT_MOTOROLA_MODE;

	else if (mode > 3)

		return dev_err_probe(&pdev->dev, -EINVAL,

		return dev_err_probe(dev, -EINVAL,

				     "invalid 'microchip,motorola-mode' value %u\n", mode);



	/*
@@ -342,9 +343,9 @@ static int mchp_corespi_probe(struct platform_device *pdev) 
	 * The hardware allows frame sizes <= APB data width.

	 * However, this driver currently only supports 8-bit frames.

	 */

	ret = of_property_read_u32(pdev->dev.of_node, "microchip,frame-size", &frame_size);

	ret = of_property_read_u32(dev->of_node, "microchip,frame-size", &frame_size);

	if (!ret && frame_size != 8)

		return dev_err_probe(&pdev->dev, -EINVAL,

		return dev_err_probe(dev, -EINVAL,

				     "CoreSPI: frame size %u not supported by this driver\n",

				     frame_size);
@@ -354,9 +355,9 @@ static int mchp_corespi_probe(struct platform_device *pdev) 
	 * To prevent CS deassertion when TX FIFO drains, the ssel-active property

	 * keeps CS asserted for the full SPI transfer.

	 */

	assert_ssel = of_property_read_bool(pdev->dev.of_node, "microchip,ssel-active");

	assert_ssel = of_property_read_bool(dev->of_node, "microchip,ssel-active");

	if (!assert_ssel)

		return dev_err_probe(&pdev->dev, -EINVAL,

		return dev_err_probe(dev, -EINVAL,

				     "hardware must enable 'microchip,ssel-active' to keep CS asserted for the SPI transfer\n");



	spi = spi_controller_get_devdata(host);
@@ -368,9 +369,9 @@ static int mchp_corespi_probe(struct platform_device *pdev) 
	host->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);

	host->transfer_one = mchp_corespi_transfer_one;

	host->set_cs = mchp_corespi_set_cs;

	host->dev.of_node = pdev->dev.of_node;

	host->dev.of_node = dev->of_node;



	ret = of_property_read_u32(pdev->dev.of_node, "fifo-depth", &spi->fifo_depth);

	ret = of_property_read_u32(dev->of_node, "fifo-depth", &spi->fifo_depth);

	if (ret)

		spi->fifo_depth = MCHP_CORESPI_DEFAULT_FIFO_DEPTH;
@@ -382,24 +383,21 @@ static int mchp_corespi_probe(struct platform_device *pdev) 
	if (spi->irq < 0)

		return spi->irq;



	ret = devm_request_irq(&pdev->dev, spi->irq, mchp_corespi_interrupt,

			       IRQF_SHARED, dev_name(&pdev->dev), host);

	ret = devm_request_irq(dev, spi->irq, mchp_corespi_interrupt, IRQF_SHARED,

			       dev_name(dev), host);

	if (ret)

		return dev_err_probe(&pdev->dev, ret,

				     "could not request irq\n");

		return dev_err_probe(dev, ret, "could not request irq\n");



	spi->clk = devm_clk_get_enabled(&pdev->dev, NULL);

	spi->clk = devm_clk_get_enabled(dev, NULL);

	if (IS_ERR(spi->clk))

		return dev_err_probe(&pdev->dev, PTR_ERR(spi->clk),

				     "could not get clk\n");

		return dev_err_probe(dev, PTR_ERR(spi->clk), "could not get clk\n");



	mchp_corespi_init(host, spi);



	ret = devm_spi_register_controller(&pdev->dev, host);

	ret = devm_spi_register_controller(dev, host);

	if (ret) {

		mchp_corespi_disable(spi);

		return dev_err_probe(&pdev->dev, ret,

				     "unable to register host for CoreSPI controller\n");

		return dev_err_probe(dev, ret, "unable to register host for CoreSPI controller\n");

	}



	return 0;