Commit 06b26738 authored by Zong-Zhe Yang's avatar Zong-Zhe Yang Committed by Kalle Valo
Browse files

wifi: rtw89: mac: get TX power control register according to chip gen 



There are two difference between Wi-Fi 6 and Wi-Fi 7 chips.
1. Address range of TX power control register
2. Checking code to get a TX power control register

So, separate the implementation of them, access according to
chip generation, and rename original things with a suffix `_ax`.

Signed-off-by: default avatarZong-Zhe Yang <kevin_yang@realtek.com>
Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: default avatarKalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20231003015446.14658-2-pkshih@realtek.com
parent f0fb62e0

drivers/net/wireless/realtek/rtw89/mac.c

+8 −6
Original line number Diff line number Diff line
@@ -4774,7 +4774,8 @@ void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 
	handler(rtwdev, skb, len);

}



bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev,

static

bool rtw89_mac_get_txpwr_cr_ax(struct rtw89_dev *rtwdev,

			       enum rtw89_phy_idx phy_idx,

			       u32 reg_base, u32 *cr)

{
@@ -4782,13 +4783,13 @@ bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev, 
	enum rtw89_qta_mode mode = dle_mem->mode;

	u32 addr = rtw89_mac_reg_by_idx(rtwdev, reg_base, phy_idx);



	if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR) {

	if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR_AX) {

		rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n",

			  addr);

		goto error;

	}



	if (addr >= CMAC1_START_ADDR && addr <= CMAC1_END_ADDR)

	if (addr >= CMAC1_START_ADDR_AX && addr <= CMAC1_END_ADDR_AX)

		if (mode == RTW89_QTA_SCC) {

			rtw89_err(rtwdev,

				  "[TXPWR] addr=0x%x but hw not enable\n",
@@ -4805,7 +4806,6 @@ bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev, 


	return false;

}

EXPORT_SYMBOL(rtw89_mac_get_txpwr_cr);



int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable)

{
@@ -5756,5 +5756,7 @@ const struct rtw89_mac_gen_def rtw89_mac_gen_ax = { 
	.fwdl_enable_wcpu = rtw89_mac_enable_cpu_ax,

	.fwdl_get_status = rtw89_fw_get_rdy_ax,

	.fwdl_check_path_ready = rtw89_fwdl_check_path_ready_ax,



	.get_txpwr_cr = rtw89_mac_get_txpwr_cr_ax,

};

EXPORT_SYMBOL(rtw89_mac_gen_ax);

drivers/net/wireless/realtek/rtw89/mac.h

+10 −6
Original line number Diff line number Diff line
@@ -865,6 +865,10 @@ struct rtw89_mac_gen_def { 
				bool dlfw, bool include_bb);

	u8 (*fwdl_get_status)(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type);

	int (*fwdl_check_path_ready)(struct rtw89_dev *rtwdev, bool h2c_or_fwdl);



	bool (*get_txpwr_cr)(struct rtw89_dev *rtwdev,

			     enum rtw89_phy_idx phy_idx,

			     u32 reg_base, u32 *cr);

};



extern const struct rtw89_mac_gen_def rtw89_mac_gen_ax;
@@ -1028,9 +1032,6 @@ u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev); 
bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev);

int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl);

int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl);

bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev,

			    enum rtw89_phy_idx phy_idx,

			    u32 reg_base, u32 *cr);

void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter);

void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev);

void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
@@ -1060,9 +1061,10 @@ static inline int rtw89_mac_txpwr_read32(struct rtw89_dev *rtwdev, 
					 enum rtw89_phy_idx phy_idx,

					 u32 reg_base, u32 *val)

{

	const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;

	u32 cr;



	if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))

	if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))

		return -EINVAL;



	*val = rtw89_read32(rtwdev, cr);
@@ -1073,9 +1075,10 @@ static inline int rtw89_mac_txpwr_write32(struct rtw89_dev *rtwdev, 
					  enum rtw89_phy_idx phy_idx,

					  u32 reg_base, u32 val)

{

	const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;

	u32 cr;



	if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))

	if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))

		return -EINVAL;



	rtw89_write32(rtwdev, cr, val);
@@ -1086,9 +1089,10 @@ static inline int rtw89_mac_txpwr_write32_mask(struct rtw89_dev *rtwdev, 
					       enum rtw89_phy_idx phy_idx,

					       u32 reg_base, u32 mask, u32 val)

{

	const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;

	u32 cr;



	if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))

	if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))

		return -EINVAL;



	rtw89_write32_mask(rtwdev, cr, mask, val);

drivers/net/wireless/realtek/rtw89/mac_be.c

+40 −0
Original line number Diff line number Diff line
@@ -205,6 +205,44 @@ static int rtw89_fwdl_check_path_ready_be(struct rtw89_dev *rtwdev, 
					rtwdev, R_BE_WCPU_FW_CTRL);

}



static bool rtw89_mac_get_txpwr_cr_be(struct rtw89_dev *rtwdev,

				      enum rtw89_phy_idx phy_idx,

				      u32 reg_base, u32 *cr)

{

	const struct rtw89_dle_mem *dle_mem = rtwdev->chip->dle_mem;

	enum rtw89_qta_mode mode = dle_mem->mode;

	int ret;



	ret = rtw89_mac_check_mac_en(rtwdev, (enum rtw89_mac_idx)phy_idx,

				     RTW89_CMAC_SEL);

	if (ret) {

		if (test_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags))

			return false;



		rtw89_err(rtwdev, "[TXPWR] check mac enable failed\n");

		return false;

	}



	if (reg_base < R_BE_PWR_MODULE || reg_base > R_BE_CMAC_FUNC_EN_C1) {

		rtw89_err(rtwdev, "[TXPWR] reg_base=0x%x exceed txpwr cr\n",

			  reg_base);

		return false;

	}



	*cr = rtw89_mac_reg_by_idx(rtwdev, reg_base, phy_idx);



	if (*cr >= CMAC1_START_ADDR_BE && *cr <= CMAC1_END_ADDR_BE) {

		if (mode == RTW89_QTA_SCC) {

			rtw89_err(rtwdev,

				  "[TXPWR] addr=0x%x but hw not enable\n",

				  *cr);

			return false;

		}

	}



	return true;

}



const struct rtw89_mac_gen_def rtw89_mac_gen_be = {

	.band1_offset = RTW89_MAC_BE_BAND_REG_OFFSET,

	.filter_model_addr = R_BE_FILTER_MODEL_ADDR,
@@ -217,5 +255,7 @@ const struct rtw89_mac_gen_def rtw89_mac_gen_be = { 
	.fwdl_enable_wcpu = rtw89_mac_fwdl_enable_wcpu_be,

	.fwdl_get_status = fwdl_get_status_be,

	.fwdl_check_path_ready = rtw89_fwdl_check_path_ready_be,



	.get_txpwr_cr = rtw89_mac_get_txpwr_cr_be,

};

EXPORT_SYMBOL(rtw89_mac_gen_be);

drivers/net/wireless/realtek/rtw89/reg.h

+40 −2
Original line number Diff line number Diff line
@@ -3585,8 +3585,8 @@ 
#define R_AX_MACID_ANT_TABLE 0xDC00

#define R_AX_MACID_ANT_TABLE_LAST 0xDDFC



#define CMAC1_START_ADDR 0xE000

#define CMAC1_END_ADDR 0xFFFF

#define CMAC1_START_ADDR_AX 0xE000

#define CMAC1_END_ADDR_AX 0xFFFF

#define R_AX_CMAC_REG_END 0xFFFF



#define R_AX_LTE_SW_CFG_1 0x0038
@@ -3740,6 +3740,38 @@ 
#define R_BE_PLE_DBG_FUN_INTF_DATA 0x9114

#define B_BE_PLE_DFI_DATA_MASK GENMASK(31, 0)



#define R_BE_CMAC_FUNC_EN 0x10000

#define R_BE_CMAC_FUNC_EN_C1 0x14000

#define B_BE_CMAC_CRPRT BIT(31)

#define B_BE_CMAC_EN BIT(30)

#define B_BE_CMAC_TXEN BIT(29)

#define B_BE_CMAC_RXEN BIT(28)

#define B_BE_FORCE_RESP_PKTCTL_GCKEN BIT(26)

#define B_BE_FORCE_SIGB_REG_GCKEN BIT(25)

#define B_BE_FORCE_POWER_REG_GCKEN BIT(23)

#define B_BE_FORCE_RMAC_REG_GCKEN BIT(22)

#define B_BE_FORCE_TRXPTCL_REG_GCKEN BIT(21)

#define B_BE_FORCE_TMAC_REG_GCKEN BIT(20)

#define B_BE_FORCE_CMAC_DMA_REG_GCKEN BIT(19)

#define B_BE_FORCE_PTCL_REG_GCKEN BIT(18)

#define B_BE_FORCE_SCHEDULER_RREG_GCKEN BIT(17)

#define B_BE_FORCE_CMAC_COMMON_REG_GCKEN BIT(16)

#define B_BE_FORCE_CMACREG_GCKEN BIT(15)

#define B_BE_TXTIME_EN BIT(8)

#define B_BE_RESP_PKTCTL_EN BIT(7)

#define B_BE_SIGB_EN BIT(6)

#define B_BE_PHYINTF_EN BIT(5)

#define B_BE_CMAC_DMA_EN BIT(4)

#define B_BE_PTCLTOP_EN BIT(3)

#define B_BE_SCHEDULER_EN BIT(2)

#define B_BE_TMAC_EN BIT(1)

#define B_BE_RMAC_EN BIT(0)

#define B_BE_CMAC_FUNC_EN_SET (B_BE_CMAC_EN | B_BE_CMAC_TXEN | B_BE_CMAC_RXEN | \

			       B_BE_PHYINTF_EN | B_BE_CMAC_DMA_EN | B_BE_PTCLTOP_EN | \

			       B_BE_SCHEDULER_EN | B_BE_TMAC_EN | B_BE_RMAC_EN | \

			       B_BE_CMAC_CRPRT | B_BE_TXTIME_EN | B_BE_RESP_PKTCTL_EN | \

			       B_BE_SIGB_EN)



#define R_BE_PORT_0_TSF_SYNC 0x102A0

#define R_BE_PORT_0_TSF_SYNC_C1 0x142A0

#define B_BE_P0_SYNC_NOW_P BIT(30)
@@ -3906,6 +3938,12 @@ 
#define B_BE_A_A1_MATCH BIT(1)

#define B_BE_SNIFFER_MODE BIT(0)



#define R_BE_PWR_MODULE 0x11900

#define R_BE_PWR_MODULE_C1 0x15900



#define CMAC1_START_ADDR_BE 0x14000

#define CMAC1_END_ADDR_BE 0x17FFF



#define RR_MOD 0x00

#define RR_MOD_V1 0x10000

#define RR_MOD_IQK GENMASK(19, 4)