Commit 06c85b58 authored by Marc Zyngier's avatar Marc Zyngier
Browse files

KVM: arm64: Move GICv5 timer PPI validation into timer_irqs_are_valid() 



Userspace can set the timer PPI numbers way before a GIC has been
created, leading to odd behaviours on GICv5 as we'd accept non
architectural PPI numbers.

Move the v5 check into timer_irqs_are_valid(), which aligns the
behaviour with the pre-v5 GICs, and is also guaranteed to run
only once a GIC has been configured.

Reviewed-by: default avatarSascha Bischoff <sascha.bischoff@arm.com>
Fixes: 9491c63b ("KVM: arm64: gic-v5: Enlighten arch timer for GICv5")
Link: https://sashiko.dev/#/patchset/20260319154937.3619520-1-sascha.bischoff%40arm.com
Link: https://patch.msgid.link/20260401103611.357092-14-maz@kernel.org


Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parent fbcbf259

arch/arm64/kvm/arch_timer.c

+4 −7
Original line number Diff line number Diff line
@@ -1543,6 +1543,10 @@ static bool timer_irqs_are_valid(struct kvm_vcpu *vcpu) 
		if (kvm_vgic_set_owner(vcpu, irq, ctx))

			break;



		/* With GICv5, the default PPI is what you get -- nothing else */

		if (vgic_is_v5(vcpu->kvm) && irq != get_vgic_ppi(vcpu->kvm, default_ppi[i]))

			break;



		/*

		 * We know by construction that we only have PPIs, so all values

		 * are less than 32 for non-GICv5 VGICs. On GICv5, they are
@@ -1678,13 +1682,6 @@ int kvm_arm_timer_set_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr) 
		return -ENXIO;

	}



	/*

	 * The PPIs for the Arch Timers are architecturally defined for

	 * GICv5. Reject anything that changes them from the specified value.

	 */

	if (vgic_is_v5(vcpu->kvm) && vcpu->kvm->arch.timer_data.ppi[idx] != irq)

		return -EINVAL;



	/*

	 * We cannot validate the IRQ unicity before we run, so take it at

	 * face value. The verdict will be given on first vcpu run, for each