Unverified Commit 06e9f5a1 authored by Miquel Raynal's avatar Miquel Raynal Committed by Mark Brown
Browse files

spi: cadence-qspi: Support per spi-mem operation frequency switches 



Every ->exec_op() call correctly configures the spi bus speed to the
maximum allowed frequency for the memory using the constant spi default
parameter. Since we can now have per-operation constraints, let's use
the value that comes from the spi-mem operation structure instead. In
case there is no specific limitation for this operation, the default spi
device value will be given anyway.

The per-operation frequency capability is thus advertised to the spi-mem
core.

Reviewed-by: default avatarTudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
Link: https://patch.msgid.link/20241224-winbond-6-11-rc1-quad-support-v2-6-ad218dbc406f@bootlin.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 5baa1897

drivers/spi/spi-cadence-quadspi.c

+2 −1
Original line number Diff line number Diff line
@@ -1409,7 +1409,7 @@ static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op) 
	struct cqspi_flash_pdata *f_pdata;



	f_pdata = &cqspi->f_pdata[spi_get_chipselect(mem->spi, 0)];

	cqspi_configure(f_pdata, mem->spi->max_speed_hz);

	cqspi_configure(f_pdata, op->max_freq);



	if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {

	/*
@@ -1658,6 +1658,7 @@ static const struct spi_controller_mem_ops cqspi_mem_ops = { 


static const struct spi_controller_mem_caps cqspi_mem_caps = {

	.dtr = true,

	.per_op_freq = true,

};



static int cqspi_setup_flash(struct cqspi_st *cqspi)