Commit 06f6516e authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-6.16-2025-25-25' of...

Merge tag 'amd-drm-fixes-6.16-2025-25-25' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-6.16-2025-25-25:

amdgpu:
- Cleaner shader support for additional GFX9 GPUs
- MES firmware compatibility fixes
- Discovery error reporting fixes
- SDMA6/7 userq fixes
- Backlight fix
- EDID sanity check

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Alex Deucher <alexander.deucher@amd.com>
Link: https://lore.kernel.org/r/20250625151734.11537-1-alexander.deucher@amd.com
parents 86731a2a 6847b3b6
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+13 −15
Original line number Diff line number Diff line
@@ -321,10 +321,12 @@ static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev,
	const struct firmware *fw;
	int r;

	r = request_firmware(&fw, fw_name, adev->dev);
	r = firmware_request_nowarn(&fw, fw_name, adev->dev);
	if (r) {
		dev_err(adev->dev, "can't load firmware \"%s\"\n",
			fw_name);
		if (amdgpu_discovery == 2)
			dev_err(adev->dev, "can't load firmware \"%s\"\n", fw_name);
		else
			drm_info(&adev->ddev, "Optional firmware \"%s\" was not found\n", fw_name);
		return r;
	}

@@ -459,16 +461,12 @@ static int amdgpu_discovery_init(struct amdgpu_device *adev)
	/* Read from file if it is the preferred option */
	fw_name = amdgpu_discovery_get_fw_name(adev);
	if (fw_name != NULL) {
		dev_info(adev->dev, "use ip discovery information from file");
		drm_dbg(&adev->ddev, "use ip discovery information from file");
		r = amdgpu_discovery_read_binary_from_file(adev, adev->mman.discovery_bin, fw_name);

		if (r) {
			dev_err(adev->dev, "failed to read ip discovery binary from file\n");
			r = -EINVAL;
		if (r)
			goto out;
		}

	} else {
		drm_dbg(&adev->ddev, "use ip discovery information from memory");
		r = amdgpu_discovery_read_binary_from_mem(
			adev, adev->mman.discovery_bin);
		if (r)
@@ -1338,10 +1336,8 @@ static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
	int r;

	r = amdgpu_discovery_init(adev);
	if (r) {
		DRM_ERROR("amdgpu_discovery_init failed\n");
	if (r)
		return r;
	}

	wafl_ver = 0;
	adev->gfx.xcc_mask = 0;
@@ -2579,8 +2575,10 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
		break;
	default:
		r = amdgpu_discovery_reg_base_init(adev);
		if (r)
			return -EINVAL;
		if (r) {
			drm_err(&adev->ddev, "discovery failed: %d\n", r);
			return r;
		}

		amdgpu_discovery_harvest_ip(adev);
		amdgpu_discovery_get_gfx_info(adev);
+19 −0
Original line number Diff line number Diff line
@@ -2235,6 +2235,25 @@ static int gfx_v9_0_sw_init(struct amdgpu_ip_block *ip_block)
	}

	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
	case IP_VERSION(9, 0, 1):
	case IP_VERSION(9, 2, 1):
	case IP_VERSION(9, 4, 0):
	case IP_VERSION(9, 2, 2):
	case IP_VERSION(9, 1, 0):
	case IP_VERSION(9, 3, 0):
		adev->gfx.cleaner_shader_ptr = gfx_9_4_2_cleaner_shader_hex;
		adev->gfx.cleaner_shader_size = sizeof(gfx_9_4_2_cleaner_shader_hex);
		if (adev->gfx.me_fw_version  >= 167 &&
		    adev->gfx.pfp_fw_version >= 196 &&
		    adev->gfx.mec_fw_version >= 474) {
			adev->gfx.enable_cleaner_shader = true;
			r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size);
			if (r) {
				adev->gfx.enable_cleaner_shader = false;
				dev_err(adev->dev, "Failed to initialize cleaner shader\n");
			}
		}
		break;
	case IP_VERSION(9, 4, 2):
		adev->gfx.cleaner_shader_ptr = gfx_9_4_2_cleaner_shader_hex;
		adev->gfx.cleaner_shader_size = sizeof(gfx_9_4_2_cleaner_shader_hex);
+6 −4
Original line number Diff line number Diff line
@@ -1630,11 +1630,13 @@ static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block)
	if (r)
		goto failure;

	if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x50) {
		r = mes_v11_0_set_hw_resources_1(&adev->mes);
		if (r) {
			DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r);
			goto failure;
		}
	}

	r = mes_v11_0_query_sched_status(&adev->mes);
	if (r) {
+2 −1
Original line number Diff line number Diff line
@@ -1742,6 +1742,7 @@ static int mes_v12_0_hw_init(struct amdgpu_ip_block *ip_block)
	if (r)
		goto failure;

	if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x4b)
		mes_v12_0_set_hw_resources_1(&adev->mes, AMDGPU_MES_SCHED_PIPE);

	mes_v12_0_init_aggregated_doorbell(&adev->mes);
+16 −3
Original line number Diff line number Diff line
@@ -1374,9 +1374,22 @@ static int sdma_v6_0_sw_init(struct amdgpu_ip_block *ip_block)
	else
		DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");

	/* add firmware version checks here */
	if (0 && !adev->sdma.disable_uq)
	switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
	case IP_VERSION(6, 0, 0):
		if ((adev->sdma.instance[0].fw_version >= 24) && !adev->sdma.disable_uq)
			adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs;
		break;
	case IP_VERSION(6, 0, 2):
		if ((adev->sdma.instance[0].fw_version >= 21) && !adev->sdma.disable_uq)
			adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs;
		break;
	case IP_VERSION(6, 0, 3):
		if ((adev->sdma.instance[0].fw_version >= 25) && !adev->sdma.disable_uq)
			adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs;
		break;
	default:
		break;
	}

	r = amdgpu_sdma_sysfs_reset_mask_init(adev);
	if (r)
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