Commit 06fbf84f authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-6.9-2024-05-10' of...

Merge tag 'amd-drm-fixes-6.9-2024-05-10' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-6.9-2024-05-10:

amdgpu:
- DCN 3.5 fix
- MST DSC fixes
- S0i3 fix
- S4 fix
- HDP MMIO mapping fix
- Fix a regression in visible vram handling

amdkfd:
- Spatial partition fix

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510171110.1394940-1-alexander.deucher@amd.com
parents fa68a34e 8d2c9307
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+1 −1
Original line number Diff line number Diff line
@@ -427,7 +427,7 @@ bool amdgpu_res_cpu_visible(struct amdgpu_device *adev,

	amdgpu_res_first(res, 0, res->size, &cursor);
	while (cursor.remaining) {
		if ((cursor.start + cursor.size) >= adev->gmc.visible_vram_size)
		if ((cursor.start + cursor.size) > adev->gmc.visible_vram_size)
			return false;
		amdgpu_res_next(&cursor, cursor.size);
	}
+5 −2
Original line number Diff line number Diff line
@@ -1139,7 +1139,7 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep,
			goto err_unlock;
		}
		offset = dev->adev->rmmio_remap.bus_addr;
		if (!offset) {
		if (!offset || (PAGE_SIZE > 4096)) {
			err = -ENOMEM;
			goto err_unlock;
		}
@@ -2307,7 +2307,7 @@ static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd,
			return -EINVAL;
		}
		offset = pdd->dev->adev->rmmio_remap.bus_addr;
		if (!offset) {
		if (!offset || (PAGE_SIZE > 4096)) {
			pr_err("amdgpu_amdkfd_get_mmio_remap_phys_addr failed\n");
			return -ENOMEM;
		}
@@ -3349,6 +3349,9 @@ static int kfd_mmio_mmap(struct kfd_node *dev, struct kfd_process *process,
	if (vma->vm_end - vma->vm_start != PAGE_SIZE)
		return -EINVAL;

	if (PAGE_SIZE > 4096)
		return -EINVAL;

	address = dev->adev->rmmio_remap.bus_addr;

	vm_flags_set(vma, VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_NORESERVE |
+2 −3
Original line number Diff line number Diff line
@@ -1997,9 +1997,8 @@ int kfd_topology_add_device(struct kfd_node *gpu)
			HSA_CAP_ASIC_REVISION_MASK);

	dev->node_props.location_id = pci_dev_id(gpu->adev->pdev);
	/* On multi-partition nodes, node id = location_id[31:28] */
	if (gpu->kfd->num_nodes > 1)
		dev->node_props.location_id |= (dev->gpu->node_id << 28);
	if (KFD_GC_VERSION(dev->gpu->kfd) == IP_VERSION(9, 4, 3))
		dev->node_props.location_id |= dev->gpu->node_id;

	dev->node_props.domain = pci_domain_nr(gpu->adev->pdev->bus);
	dev->node_props.max_engine_clk_fcompute =
+13 −3
Original line number Diff line number Diff line
@@ -1219,8 +1219,10 @@ static bool is_dsc_need_re_compute(
	if (dc_link->type != dc_connection_mst_branch)
		return false;

	if (!(dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT ||
		dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT))
	/* add a check for older MST DSC with no virtual DPCDs */
	if (needs_dsc_aux_workaround(dc_link)  &&
		(!(dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT ||
		dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT)))
		return false;

	for (i = 0; i < MAX_PIPES; i++)
@@ -1240,7 +1242,15 @@ static bool is_dsc_need_re_compute(
			continue;

		aconnector = (struct amdgpu_dm_connector *) stream->dm_stream_context;
		if (!aconnector)
		if (!aconnector || !aconnector->dsc_aux)
			continue;

		/*
		 *	check if cached virtual MST DSC caps are available and DSC is supported
		 *	as per specifications in their Virtual DPCD registers.
		*/
		if (!(aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported ||
			aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT))
			continue;

		stream_on_link[new_stream_on_link_num] = aconnector;
+2 −2
Original line number Diff line number Diff line
@@ -195,9 +195,9 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc = {
	.dcn_downspread_percent = 0.5,
	.gpuvm_min_page_size_bytes = 4096,
	.hostvm_min_page_size_bytes = 4096,
	.do_urgent_latency_adjustment = 0,
	.do_urgent_latency_adjustment = 1,
	.urgent_latency_adjustment_fabric_clock_component_us = 0,
	.urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
	.urgent_latency_adjustment_fabric_clock_reference_mhz = 3000,
};

void dcn35_build_wm_range_table_fpu(struct clk_mgr *clk_mgr)
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