Commit 0701117e authored by Alvin Lee's avatar Alvin Lee Committed by Alex Deucher
Browse files

Revert "drm/amd/display: For FPO and SubVP/DRR configs program vmin/max sel" 



This reverts commit 6b2b782a.

Since, it was causing regression for some DRR scenarios.

Reviewed-by: default avatarAric Cyr <aric.cyr@amd.com>
Reviewed-by: default avatarNevenko Stupar <nevenko.stupar@amd.com>
Acked-by: default avatarHamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: default avatarAlvin Lee <alvin.lee2@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 84d2ae7c

drivers/gpu/drm/amd/display/dc/core/dc.c

+9 −36
Original line number Diff line number Diff line
@@ -411,12 +411,9 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc, 
	 * avoid conflicting with firmware updates.

	 */

	if (dc->ctx->dce_version > DCE_VERSION_MAX)

		if (dc->optimized_required)

		if (dc->optimized_required || dc->wm_optimized_required)

			return false;



	if (!memcmp(&stream->adjust, adjust, sizeof(*adjust)))

		return true;



	dc_exit_ips_for_hw_access(dc);



	stream->adjust.v_total_max = adjust->v_total_max;
@@ -2256,6 +2253,7 @@ void dc_post_update_surfaces_to_stream(struct dc *dc) 
	}



	dc->optimized_required = false;

	dc->wm_optimized_required = false;

}



bool dc_set_generic_gpio_for_stereo(bool enable,
@@ -2678,6 +2676,8 @@ enum surface_update_type dc_check_update_surfaces_for_stream( 
		} else if (memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0) {

			dc->optimized_required = true;

		}



		dc->optimized_required |= dc->wm_optimized_required;

	}



	return type;
@@ -2885,6 +2885,9 @@ static void copy_stream_update_to_stream(struct dc *dc, 
	if (update->vrr_active_fixed)

		stream->vrr_active_fixed = *update->vrr_active_fixed;



	if (update->crtc_timing_adjust)

		stream->adjust = *update->crtc_timing_adjust;



	if (update->dpms_off)

		stream->dpms_off = *update->dpms_off;
@@ -3513,33 +3516,6 @@ static void wait_for_outstanding_hw_updates(struct dc *dc, const struct dc_state 
	}

}



static void update_drr_for_full_update(struct dc *dc, struct dc_state *context)

{

	uint32_t i;



	for (i = 0; i < dc->res_pool->pipe_count; i++) {

		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

		struct dc_stream_state *stream = pipe->stream;

		struct timing_generator *tg = pipe->stream_res.tg;

		struct drr_params params = {0};



		/* pipe not in use */

		if (!resource_is_pipe_type(pipe, OTG_MASTER))

			continue;



		/* skip phantom pipes */

		if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM)

			continue;



		params.vertical_total_min = stream->adjust.v_total_min;

		params.vertical_total_max = stream->adjust.v_total_max;

		params.vertical_total_mid = stream->adjust.v_total_mid;

		params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num;

		if (pipe->stream_res.tg->funcs->set_drr)

			tg->funcs->set_drr(pipe->stream_res.tg, &params);

	}

}



static void commit_planes_for_stream(struct dc *dc,

		struct dc_surface_update *srf_updates,

		int surface_count,
@@ -3909,10 +3885,6 @@ static void commit_planes_for_stream(struct dc *dc, 
			pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);

	}



	// Update DRR for all pipes

	if (update_type != UPDATE_TYPE_FAST)

		update_drr_for_full_update(dc, context);



	current_stream_mask = get_stream_mask(dc, context);

	if (current_stream_mask != context->stream_mask) {

		context->stream_mask = current_stream_mask;
@@ -4353,7 +4325,8 @@ static bool full_update_required(struct dc *dc, 
			stream_update->mst_bw_update ||

			stream_update->func_shaper ||

			stream_update->lut3d_func ||

			stream_update->pending_test_pattern))

			stream_update->pending_test_pattern ||

			stream_update->crtc_timing_adjust))

		return true;



	if (stream) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

+0 −14
Original line number Diff line number Diff line
@@ -5027,20 +5027,6 @@ enum dc_status update_dp_encoder_resources_for_test_harness(const struct dc *dc, 
	return DC_OK;

}



bool resource_subvp_in_use(struct dc *dc,

		struct dc_state *context)

{

	uint32_t i;



	for (i = 0; i < dc->res_pool->pipe_count; i++) {

		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];



		if (dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_NONE)

			return true;

	}

	return false;

}



bool check_subvp_sw_cursor_fallback_req(const struct dc *dc, struct dc_stream_state *stream)

{

	if (!dc->debug.disable_subvp_high_refresh && is_subvp_high_refresh_candidate(stream))

drivers/gpu/drm/amd/display/dc/dc.h

+1 −0
Original line number Diff line number Diff line
@@ -1039,6 +1039,7 @@ struct dc { 


	/* Require to optimize clocks and bandwidth for added/removed planes */

	bool optimized_required;

	bool wm_optimized_required;

	bool idle_optimizations_allowed;

	bool enable_c20_dtm_b0;

drivers/gpu/drm/amd/display/dc/dc_stream.h

+2 −0
Original line number Diff line number Diff line
@@ -139,6 +139,7 @@ union stream_update_flags { 
		uint32_t wb_update:1;

		uint32_t dsc_changed : 1;

		uint32_t mst_bw : 1;

		uint32_t crtc_timing_adjust : 1;

		uint32_t fams_changed : 1;

	} bits;
@@ -325,6 +326,7 @@ struct dc_stream_update { 
	struct dc_3dlut *lut3d_func;



	struct test_pattern *pending_test_pattern;

	struct dc_crtc_timing_adjust *crtc_timing_adjust;

};



bool dc_is_stream_unchanged(

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c

+14 −0
Original line number Diff line number Diff line
@@ -183,6 +183,20 @@ bool dcn32_all_pipes_have_stream_and_plane(struct dc *dc, 
	return true;

}



bool dcn32_subvp_in_use(struct dc *dc,

		struct dc_state *context)

{

	uint32_t i;



	for (i = 0; i < dc->res_pool->pipe_count; i++) {

		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];



		if (dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_NONE)

			return true;

	}

	return false;

}



bool dcn32_mpo_in_use(struct dc_state *context)

{

	uint32_t i;