Commit 07025b51 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'riscv-for-linus-6.19-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V updates from Paul Walmsley:

 - Enable parallel hotplug for RISC-V

 - Optimize vector regset allocation for ptrace()

 - Add a kernel selftest for the vector ptrace interface

 - Enable the userspace RAID6 test to build and run using RISC-V vectors

 - Add initial support for the Zalasr RISC-V ratified ISA extension

 - For the Zicbop RISC-V ratified ISA extension to userspace, expose
   hardware and kernel support to userspace and add a kselftest for
   Zicbop

 - Convert open-coded instances of 'asm goto's that are controlled by
   runtime ALTERNATIVEs to use riscv_has_extension_{un,}likely(),
   following arm64's alternative_has_cap_{un,}likely()

 - Remove an unnecessary mask in the GFP flags used in some calls to
   pagetable_alloc()

* tag 'riscv-for-linus-6.19-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  selftests/riscv: Add Zicbop prefetch test
  riscv: hwprobe: Expose Zicbop extension and its block size
  riscv: Introduce Zalasr instructions
  riscv: hwprobe: Export Zalasr extension
  dt-bindings: riscv: Add Zalasr ISA extension description
  riscv: Add ISA extension parsing for Zalasr
  selftests: riscv: Add test for the Vector ptrace interface
  riscv: ptrace: Optimize the allocation of vector regset
  raid6: test: Add support for RISC-V
  raid6: riscv: Allow code to be compiled in userspace
  raid6: riscv: Prevent compiler from breaking inline vector assembly code
  riscv: cmpxchg: Use riscv_has_extension_likely
  riscv: bitops: Use riscv_has_extension_likely
  riscv: hweight: Use riscv_has_extension_likely
  riscv: checksum: Use riscv_has_extension_likely
  riscv: pgtable: Use riscv_has_extension_unlikely
  riscv: Remove __GFP_HIGHMEM masking
  RISC-V: Enable HOTPLUG_PARALLEL for secondary CPUs
parents ad952db4 a131fd60
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+10 −1
Original line number Diff line number Diff line
@@ -249,6 +249,9 @@ The following keys are defined:
       defined in the in the RISC-V ISA manual starting from commit e87412e621f1
       ("integrate Zaamo and Zalrsc text (#1304)").

  * :c:macro:`RISCV_HWPROBE_EXT_ZALASR`: The Zalasr extension is supported as
       frozen at commit 194f0094 ("Version 0.9 for freeze") of riscv-zalasr.

  * :c:macro:`RISCV_HWPROBE_EXT_ZALRSC`: The Zalrsc extension is supported as
       defined in the in the RISC-V ISA manual starting from commit e87412e621f1
       ("integrate Zaamo and Zalrsc text (#1304)").
@@ -275,6 +278,9 @@ The following keys are defined:
       ratified in commit 49f49c842ff9 ("Update to Rafified state") of
       riscv-zabha.

  * :c:macro:`RISCV_HWPROBE_EXT_ZICBOP`: The Zicbop extension is supported, as
       ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.

* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated.  Returns similar values to
     :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was
     mistakenly classified as a bitmask rather than a value.
@@ -370,3 +376,6 @@ The following keys are defined:
    * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ`: The Xsfvfwmaccqqq
        vendor extension is supported in version 1.0 of Matrix Multiply Accumulate
	Instruction Extensions Specification.

* :c:macro:`RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE`: An unsigned int which
  represents the size of the Zicbop block in bytes.
+5 −0
Original line number Diff line number Diff line
@@ -248,6 +248,11 @@ properties:
            is supported as ratified at commit 5059e0ca641c ("update to
            ratified") of the riscv-zacas.

        - const: zalasr
          description: |
            The standard Zalasr extension for load-acquire/store-release as frozen
            at commit 194f0094 ("Version 0.9 for freeze") of riscv-zalasr.

        - const: zalrsc
          description: |
            The standard Zalrsc extension for load-reserved/store-conditional as
+1 −1
Original line number Diff line number Diff line
@@ -200,7 +200,7 @@ config RISCV
	select HAVE_SAMPLE_FTRACE_DIRECT_MULTI
	select HAVE_STACKPROTECTOR
	select HAVE_SYSCALL_TRACEPOINTS
	select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU
	select HOTPLUG_PARALLEL if HOTPLUG_CPU
	select IRQ_DOMAIN
	select IRQ_FORCED_THREADING
	select KASAN_VMALLOC if KASAN
+8 −16
Original line number Diff line number Diff line
@@ -19,10 +19,10 @@

static __always_inline unsigned int __arch_hweight32(unsigned int w)
{
#if defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB)
	asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0,
				      RISCV_ISA_EXT_ZBB, 1)
			  : : : : legacy);
	if (!(IS_ENABLED(CONFIG_RISCV_ISA_ZBB) &&
	      IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB) &&
	      riscv_has_extension_likely(RISCV_ISA_EXT_ZBB)))
		return __sw_hweight32(w);

	asm (".option push\n"
	     ".option arch,+zbb\n"
@@ -31,10 +31,6 @@ static __always_inline unsigned int __arch_hweight32(unsigned int w)
	     : "=r" (w) : "r" (w) :);

	return w;

legacy:
#endif
	return __sw_hweight32(w);
}

static inline unsigned int __arch_hweight16(unsigned int w)
@@ -50,10 +46,10 @@ static inline unsigned int __arch_hweight8(unsigned int w)
#if BITS_PER_LONG == 64
static __always_inline unsigned long __arch_hweight64(__u64 w)
{
#if defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB)
	asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0,
				      RISCV_ISA_EXT_ZBB, 1)
			  : : : : legacy);
	if (!(IS_ENABLED(CONFIG_RISCV_ISA_ZBB) &&
	      IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB) &&
	      riscv_has_extension_likely(RISCV_ISA_EXT_ZBB)))
		return __sw_hweight64(w);

	asm (".option push\n"
	     ".option arch,+zbb\n"
@@ -62,10 +58,6 @@ static __always_inline unsigned long __arch_hweight64(__u64 w)
	     : "=r" (w) : "r" (w) :);

	return w;

legacy:
#endif
	return __sw_hweight64(w);
}
#else /* BITS_PER_LONG == 64 */
static inline unsigned long __arch_hweight64(__u64 w)
+8 −24
Original line number Diff line number Diff line
@@ -47,9 +47,8 @@

static __always_inline __attribute_const__ unsigned long variable__ffs(unsigned long word)
{
	asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0,
				      RISCV_ISA_EXT_ZBB, 1)
			  : : : : legacy);
	if (!riscv_has_extension_likely(RISCV_ISA_EXT_ZBB))
		return generic___ffs(word);

	asm volatile (".option push\n"
		      ".option arch,+zbb\n"
@@ -58,9 +57,6 @@ static __always_inline __attribute_const__ unsigned long variable__ffs(unsigned
		      : "=r" (word) : "r" (word) :);

	return word;

legacy:
	return generic___ffs(word);
}

/**
@@ -76,9 +72,8 @@ static __always_inline __attribute_const__ unsigned long variable__ffs(unsigned

static __always_inline __attribute_const__ unsigned long variable__fls(unsigned long word)
{
	asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0,
				      RISCV_ISA_EXT_ZBB, 1)
			  : : : : legacy);
	if (!riscv_has_extension_likely(RISCV_ISA_EXT_ZBB))
		return generic___fls(word);

	asm volatile (".option push\n"
		      ".option arch,+zbb\n"
@@ -87,9 +82,6 @@ static __always_inline __attribute_const__ unsigned long variable__fls(unsigned
		      : "=r" (word) : "r" (word) :);

	return BITS_PER_LONG - 1 - word;

legacy:
	return generic___fls(word);
}

/**
@@ -105,9 +97,8 @@ static __always_inline __attribute_const__ unsigned long variable__fls(unsigned

static __always_inline __attribute_const__ int variable_ffs(int x)
{
	asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0,
				      RISCV_ISA_EXT_ZBB, 1)
			  : : : : legacy);
	if (!riscv_has_extension_likely(RISCV_ISA_EXT_ZBB))
		return generic_ffs(x);

	if (!x)
		return 0;
@@ -119,9 +110,6 @@ static __always_inline __attribute_const__ int variable_ffs(int x)
		      : "=r" (x) : "r" (x) :);

	return x + 1;

legacy:
	return generic_ffs(x);
}

/**
@@ -137,9 +125,8 @@ static __always_inline __attribute_const__ int variable_ffs(int x)

static __always_inline int variable_fls(unsigned int x)
{
	asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0,
				      RISCV_ISA_EXT_ZBB, 1)
			  : : : : legacy);
	if (!riscv_has_extension_likely(RISCV_ISA_EXT_ZBB))
		return generic_fls(x);

	if (!x)
		return 0;
@@ -151,9 +138,6 @@ static __always_inline int variable_fls(unsigned int x)
		      : "=r" (x) : "r" (x) :);

	return 32 - x;

legacy:
	return generic_fls(x);
}

/**
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