Commit 070e2462 authored by Phil Edworthy's avatar Phil Edworthy Committed by Greg Kroah-Hartman
Browse files

serial: 8250: dw: Improve RZN1 support 



Renesas RZ/N1 SoC features a slightly modified DW UART.

On this SoC, the CPR register value is known but not synthetized in
hardware. We hence need to provide a CPR value in the platform
data. This version of the controller also relies on acting as flow
controller when using DMA, so we need to provide the
"is dma flow controller" quirk.

Co-developed-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: default avatarPhil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/r/20220422180615.9098-10-miquel.raynal@bootlin.com


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent aa63d786

drivers/tty/serial/8250/8250_dw.c

+2 −0
Original line number Diff line number Diff line
@@ -761,6 +761,8 @@ static const struct dw8250_platform_data dw8250_armada_38x_data = { 


static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {

	.usr_reg = DW_UART_USR,

	.cpr_val = 0x00012f32,

	.quirks = DW_UART_QUIRK_IS_DMA_FC,

};



static const struct dw8250_platform_data dw8250_starfive_jh7100_data = {