Commit 07437917 authored by Uma Shankar's avatar Uma Shankar
Browse files

drm/i915: Remove i915_reg.h from intel_display.c 



Move CHICKEN_PIPESL_1 register definition to display header.
This allows intel_display.c free of i915_reg.h include.

v3: Fix commit header (Jani)

v2: Drop common header in include and use display_regs.h (Jani)

Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarUma Shankar <uma.shankar@intel.com>
Link: https://patch.msgid.link/20260205094341.1882816-10-uma.shankar@intel.com
parent f0702380

drivers/gpu/drm/i915/display/intel_display.c

+0 −1
Original line number Diff line number Diff line
@@ -50,7 +50,6 @@ 
#include "g4x_hdmi.h"

#include "hsw_ips.h"

#include "i915_config.h"

#include "i915_reg.h"

#include "i9xx_plane.h"

#include "i9xx_plane_regs.h"

#include "i9xx_wm.h"

drivers/gpu/drm/i915/display/intel_display_regs.h

+23 −0
Original line number Diff line number Diff line
@@ -1543,6 +1543,29 @@ 
#define   CHICKEN_FBC_STRIDE_MASK	REG_GENMASK(12, 0)

#define   CHICKEN_FBC_STRIDE(x)		REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x))



#define _CHICKEN_PIPESL_1_A	0x420b0

#define _CHICKEN_PIPESL_1_B	0x420b4

#define CHICKEN_PIPESL_1(pipe)	_MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)

#define   HSW_PRI_STRETCH_MAX_MASK	REG_GENMASK(28, 27)

#define   HSW_PRI_STRETCH_MAX_X8	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0)

#define   HSW_PRI_STRETCH_MAX_X4	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1)

#define   HSW_PRI_STRETCH_MAX_X2	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2)

#define   HSW_PRI_STRETCH_MAX_X1	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3)

#define   HSW_SPR_STRETCH_MAX_MASK	REG_GENMASK(26, 25)

#define   HSW_SPR_STRETCH_MAX_X8	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0)

#define   HSW_SPR_STRETCH_MAX_X4	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1)

#define   HSW_SPR_STRETCH_MAX_X2	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2)

#define   HSW_SPR_STRETCH_MAX_X1	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3)

#define   HSW_FBCQ_DIS			REG_BIT(22)

#define   HSW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(15) /* hsw */

#define   SKL_PSR_MASK_PLANE_FLIP	REG_BIT(11) /* skl+ */

#define   SKL_PLANE1_STRETCH_MAX_MASK	REG_GENMASK(1, 0)

#define   SKL_PLANE1_STRETCH_MAX_X8	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0)

#define   SKL_PLANE1_STRETCH_MAX_X4	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1)

#define   SKL_PLANE1_STRETCH_MAX_X2	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2)

#define   SKL_PLANE1_STRETCH_MAX_X1	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3)

#define   BDW_UNMASK_VBL_TO_REGS_IN_SRD	REG_BIT(0) /* bdw */



#define _CHICKEN_TRANS_A	0x420c0

#define _CHICKEN_TRANS_B	0x420c4

#define _CHICKEN_TRANS_C	0x420c8

drivers/gpu/drm/i915/i915_reg.h

+0 −22
Original line number Diff line number Diff line
@@ -878,28 +878,6 @@ 
#define CHICKEN_PAR2_1		_MMIO(0x42090)

#define   KVM_CONFIG_CHANGE_NOTIFICATION_SELECT	REG_BIT(14)



#define _CHICKEN_PIPESL_1_A	0x420b0

#define _CHICKEN_PIPESL_1_B	0x420b4

#define CHICKEN_PIPESL_1(pipe)	_MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)

#define   HSW_PRI_STRETCH_MAX_MASK	REG_GENMASK(28, 27)

#define   HSW_PRI_STRETCH_MAX_X8	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0)

#define   HSW_PRI_STRETCH_MAX_X4	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1)

#define   HSW_PRI_STRETCH_MAX_X2	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2)

#define   HSW_PRI_STRETCH_MAX_X1	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3)

#define   HSW_SPR_STRETCH_MAX_MASK	REG_GENMASK(26, 25)

#define   HSW_SPR_STRETCH_MAX_X8	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0)

#define   HSW_SPR_STRETCH_MAX_X4	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1)

#define   HSW_SPR_STRETCH_MAX_X2	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2)

#define   HSW_SPR_STRETCH_MAX_X1	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3)

#define   HSW_FBCQ_DIS			REG_BIT(22)

#define   HSW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(15) /* hsw */

#define   SKL_PSR_MASK_PLANE_FLIP	REG_BIT(11) /* skl+ */

#define   SKL_PLANE1_STRETCH_MAX_MASK	REG_GENMASK(1, 0)

#define   SKL_PLANE1_STRETCH_MAX_X8	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0)

#define   SKL_PLANE1_STRETCH_MAX_X4	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1)

#define   SKL_PLANE1_STRETCH_MAX_X2	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2)

#define   SKL_PLANE1_STRETCH_MAX_X1	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3)

#define   BDW_UNMASK_VBL_TO_REGS_IN_SRD	REG_BIT(0) /* bdw */



#define DISP_ARB_CTL	_MMIO(0x45000)

#define   DISP_FBC_MEMORY_WAKE		REG_BIT(31)