Unverified Commit 075fde58 authored by Palmer Dabbelt's avatar Palmer Dabbelt
Browse files

Merge patch series "riscv: Userspace pointer masking and tagged address ABI" 

Samuel Holland <samuel.holland@sifive.com> says:

RISC-V defines three extensions for pointer masking[1]:
 - Smmpm: configured in M-mode, affects M-mode
 - Smnpm: configured in M-mode, affects the next lower mode (S or U-mode)
 - Ssnpm: configured in S-mode, affects the next lower mode (VS, VU, or U-mode)

This series adds support for configuring Smnpm or Ssnpm (depending on
which privilege mode the kernel is running in) to allow pointer masking
in userspace (VU or U-mode), extending the PR_SET_TAGGED_ADDR_CTRL API
from arm64. Unlike arm64 TBI, userspace pointer masking is not enabled
by default on RISC-V. Additionally, the tag width (referred to as PMLEN)
is variable, so userspace needs to ask the kernel for a specific tag
width, which is interpreted as a lower bound on the number of tag bits.

This series also adds support for a tagged address ABI similar to arm64
and x86. Since accesses from the kernel to user memory use the kernel's
pointer masking configuration, not the user's, the kernel must untag
user pointers in software before dereferencing them. And since the tag
width is variable, as with LAM on x86, it must be kept the same across
all threads in a process so untagged_addr_remote() can work.

[1]: https://github.com/riscv/riscv-j-extension/raw/d70011dde6c2/zjpm-spec.pdf

* b4-shazam-merge:
  KVM: riscv: selftests: Add Smnpm and Ssnpm to get-reg-list test
  RISC-V: KVM: Allow Smnpm and Ssnpm extensions for guests
  riscv: hwprobe: Export the Supm ISA extension
  riscv: selftests: Add a pointer masking test
  riscv: Allow ptrace control of the tagged address ABI
  riscv: Add support for the tagged address ABI
  riscv: Add support for userspace pointer masking
  riscv: Add CSR definitions for pointer masking
  riscv: Add ISA extension parsing for pointer masking
  dt-bindings: riscv: Add pointer masking ISA extensions

Link: https://lore.kernel.org/r/20241016202814.4061541-1-samuel.holland@sifive.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parents ce16531d 036a1407

Documentation/arch/riscv/hwprobe.rst

+3 −0
Original line number Diff line number Diff line
@@ -239,6 +239,9 @@ The following keys are defined: 
       ratified in commit 98918c844281 ("Merge pull request #1217 from

       riscv/zawrs") of riscv-isa-manual.



  * :c:macro:`RISCV_HWPROBE_EXT_SUPM`: The Supm extension is supported as

       defined in version 1.0 of the RISC-V Pointer Masking extensions.



* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated.  Returns similar values to

     :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was

     mistakenly classified as a bitmask rather than a value.

Documentation/arch/riscv/uabi.rst

+16 −0
Original line number Diff line number Diff line
@@ -68,3 +68,19 @@ Misaligned accesses 
Misaligned scalar accesses are supported in userspace, but they may perform

poorly.  Misaligned vector accesses are only supported if the Zicclsm extension

is supported.



Pointer masking

---------------



Support for pointer masking in userspace (the Supm extension) is provided via

the ``PR_SET_TAGGED_ADDR_CTRL`` and ``PR_GET_TAGGED_ADDR_CTRL`` ``prctl()``

operations. Pointer masking is disabled by default. To enable it, userspace

must call ``PR_SET_TAGGED_ADDR_CTRL`` with the ``PR_PMLEN`` field set to the

number of mask/tag bits needed by the application. ``PR_PMLEN`` is interpreted

as a lower bound; if the kernel is unable to satisfy the request, the

``PR_SET_TAGGED_ADDR_CTRL`` operation will fail. The actual number of tag bits

is returned in ``PR_PMLEN`` by the ``PR_GET_TAGGED_ADDR_CTRL`` operation.



Additionally, when pointer masking is enabled (``PR_PMLEN`` is greater than 0),

a tagged address ABI is supported, with the same interface and behavior as

documented for AArch64 (Documentation/arch/arm64/tagged-address-abi.rst).

Documentation/devicetree/bindings/riscv/extensions.yaml

+18 −0
Original line number Diff line number Diff line
@@ -128,6 +128,18 @@ properties: 
            changes to interrupts as frozen at commit ccbddab ("Merge pull

            request #42 from riscv/jhauser-2023-RC4") of riscv-aia.



        - const: smmpm

          description: |

            The standard Smmpm extension for M-mode pointer masking as

            ratified at commit d70011dde6c2 ("Update to ratified state")

            of riscv-j-extension.



        - const: smnpm

          description: |

            The standard Smnpm extension for next-mode pointer masking as

            ratified at commit d70011dde6c2 ("Update to ratified state")

            of riscv-j-extension.



        - const: smstateen

          description: |

            The standard Smstateen extension for controlling access to CSRs
@@ -147,6 +159,12 @@ properties: 
            and mode-based filtering as ratified at commit 01d1df0 ("Add ability

            to manually trigger workflow. (#2)") of riscv-count-overflow.



        - const: ssnpm

          description: |

            The standard Ssnpm extension for next-mode pointer masking as

            ratified at commit d70011dde6c2 ("Update to ratified state")

            of riscv-j-extension.



        - const: sstc

          description: |

            The standard Sstc supervisor-level extension for time compare as

arch/riscv/Kconfig

+11 −0
Original line number Diff line number Diff line
@@ -531,6 +531,17 @@ config RISCV_ISA_C 


	  If you don't know what to do here, say Y.



config RISCV_ISA_SUPM

	bool "Supm extension for userspace pointer masking"

	depends on 64BIT

	default y

	help

	  Add support for pointer masking in userspace (Supm) when the

	  underlying hardware extension (Smnpm or Ssnpm) is detected at boot.



	  If this option is disabled, userspace will be unable to use

	  the prctl(PR_{SET,GET}_TAGGED_ADDR_CTRL) API.



config RISCV_ISA_SVNAPOT

	bool "Svnapot extension support for supervisor mode NAPOT pages"

	depends on 64BIT && MMU

arch/riscv/include/asm/csr.h

+16 −0
Original line number Diff line number Diff line
@@ -119,6 +119,10 @@ 


/* HSTATUS flags */

#ifdef CONFIG_64BIT

#define HSTATUS_HUPMM		_AC(0x3000000000000, UL)

#define HSTATUS_HUPMM_PMLEN_0	_AC(0x0000000000000, UL)

#define HSTATUS_HUPMM_PMLEN_7	_AC(0x2000000000000, UL)

#define HSTATUS_HUPMM_PMLEN_16	_AC(0x3000000000000, UL)

#define HSTATUS_VSXL		_AC(0x300000000, UL)

#define HSTATUS_VSXL_SHIFT	32

#endif
@@ -195,6 +199,10 @@ 
/* xENVCFG flags */

#define ENVCFG_STCE			(_AC(1, ULL) << 63)

#define ENVCFG_PBMTE			(_AC(1, ULL) << 62)

#define ENVCFG_PMM			(_AC(0x3, ULL) << 32)

#define ENVCFG_PMM_PMLEN_0		(_AC(0x0, ULL) << 32)

#define ENVCFG_PMM_PMLEN_7		(_AC(0x2, ULL) << 32)

#define ENVCFG_PMM_PMLEN_16		(_AC(0x3, ULL) << 32)

#define ENVCFG_CBZE			(_AC(1, UL) << 7)

#define ENVCFG_CBCFE			(_AC(1, UL) << 6)

#define ENVCFG_CBIE_SHIFT		4
@@ -216,6 +224,12 @@ 
#define SMSTATEEN0_SSTATEEN0_SHIFT	63

#define SMSTATEEN0_SSTATEEN0		(_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT)



/* mseccfg bits */

#define MSECCFG_PMM			ENVCFG_PMM

#define MSECCFG_PMM_PMLEN_0		ENVCFG_PMM_PMLEN_0

#define MSECCFG_PMM_PMLEN_7		ENVCFG_PMM_PMLEN_7

#define MSECCFG_PMM_PMLEN_16		ENVCFG_PMM_PMLEN_16



/* symbolic CSR names: */

#define CSR_CYCLE		0xc00

#define CSR_TIME		0xc01
@@ -382,6 +396,8 @@ 
#define CSR_MIP			0x344

#define CSR_PMPCFG0		0x3a0

#define CSR_PMPADDR0		0x3b0

#define CSR_MSECCFG		0x747

#define CSR_MSECCFGH		0x757

#define CSR_MVENDORID		0xf11

#define CSR_MARCHID		0xf12

#define CSR_MIMPID		0xf13