x86/pconfig: Remove unused MKTME pconfig code

#ifndef	_ASM_X86_INTEL_PCONFIG_H

#define	_ASM_X86_INTEL_PCONFIG_H

#include <asm/asm.h>

#include <asm/processor.h>

enum pconfig_target {

	INVALID_TARGET	= 0,

	MKTME_TARGET	= 1,

	PCONFIG_TARGET_NR

};

int pconfig_target_supported(enum pconfig_target target);

enum pconfig_leaf {

	MKTME_KEY_PROGRAM	= 0,

	PCONFIG_LEAF_INVALID,

};

#define PCONFIG ".byte 0x0f, 0x01, 0xc5"

/* Defines and structure for MKTME_KEY_PROGRAM of PCONFIG instruction */

/* mktme_key_program::keyid_ctrl COMMAND, bits [7:0] */

#define MKTME_KEYID_SET_KEY_DIRECT	0

#define MKTME_KEYID_SET_KEY_RANDOM	1

#define MKTME_KEYID_CLEAR_KEY		2

#define MKTME_KEYID_NO_ENCRYPT		3

/* mktme_key_program::keyid_ctrl ENC_ALG, bits [23:8] */

#define MKTME_AES_XTS_128	(1 << 8)

/* Return codes from the PCONFIG MKTME_KEY_PROGRAM */

#define MKTME_PROG_SUCCESS	0

#define MKTME_INVALID_PROG_CMD	1

#define MKTME_ENTROPY_ERROR	2

#define MKTME_INVALID_KEYID	3

#define MKTME_INVALID_ENC_ALG	4

#define MKTME_DEVICE_BUSY	5

/* Hardware requires the structure to be 256 byte aligned. Otherwise #GP(0). */

struct mktme_key_program {

	u16 keyid;

	u32 keyid_ctrl;

	u8 __rsvd[58];

	u8 key_field_1[64];

	u8 key_field_2[64];

} __packed __aligned(256);

static inline int mktme_key_program(struct mktme_key_program *key_program)

{

	unsigned long rax = MKTME_KEY_PROGRAM;

	if (!pconfig_target_supported(MKTME_TARGET))

		return -ENXIO;

	asm volatile(PCONFIG

		: "=a" (rax), "=b" (key_program)

		: "0" (rax), "1" (key_program)

		: "memory", "cc");

	return rax;

}

#endif	/* _ASM_X86_INTEL_PCONFIG_H */

obj-$(CONFIG_IA32_FEAT_CTL)		+= feat_ctl.o

ifdef CONFIG_CPU_SUP_INTEL

obj-y					+= intel.o intel_pconfig.o tsx.o

obj-y					+= intel.o tsx.o

obj-$(CONFIG_PM)			+= intel_epb.o

endif

obj-$(CONFIG_CPU_SUP_AMD)		+= amd.o

// SPDX-License-Identifier: GPL-2.0

/*

 * Intel PCONFIG instruction support.

 *

 * Copyright (C) 2017 Intel Corporation

 *

 * Author:

 *	Kirill A. Shutemov <kirill.shutemov@linux.intel.com>

 */

#include <linux/bug.h>

#include <linux/limits.h>

#include <asm/cpufeature.h>

#include <asm/intel_pconfig.h>

#define	PCONFIG_CPUID			0x1b

#define PCONFIG_CPUID_SUBLEAF_MASK	((1 << 12) - 1)

/* Subleaf type (EAX) for PCONFIG CPUID leaf (0x1B) */

enum {

	PCONFIG_CPUID_SUBLEAF_INVALID	= 0,

	PCONFIG_CPUID_SUBLEAF_TARGETID	= 1,

};

/* Bitmask of supported targets */

static u64 targets_supported __read_mostly;

int pconfig_target_supported(enum pconfig_target target)

{

	/*

	 * We would need to re-think the implementation once we get > 64

	 * PCONFIG targets. Spec allows up to 2^32 targets.

	 */

	BUILD_BUG_ON(PCONFIG_TARGET_NR >= 64);

	if (WARN_ON_ONCE(target >= 64))

		return 0;

	return targets_supported & (1ULL << target);

}

static int __init intel_pconfig_init(void)

{

	int subleaf;

	if (!boot_cpu_has(X86_FEATURE_PCONFIG))

		return 0;

	/*

	 * Scan subleafs of PCONFIG CPUID leaf.

	 *

	 * Subleafs of the same type need not to be consecutive.

	 *

	 * Stop on the first invalid subleaf type. All subleafs after the first

	 * invalid are invalid too.

	 */

	for (subleaf = 0; subleaf < INT_MAX; subleaf++) {

		struct cpuid_regs regs;

		cpuid_count(PCONFIG_CPUID, subleaf,

				&regs.eax, &regs.ebx, &regs.ecx, &regs.edx);

		switch (regs.eax & PCONFIG_CPUID_SUBLEAF_MASK) {

		case PCONFIG_CPUID_SUBLEAF_INVALID:

			/* Stop on the first invalid subleaf */

			goto out;

		case PCONFIG_CPUID_SUBLEAF_TARGETID:

			/* Mark supported PCONFIG targets */

			if (regs.ebx < 64)

				targets_supported |= (1ULL << regs.ebx);

			if (regs.ecx < 64)

				targets_supported |= (1ULL << regs.ecx);

			if (regs.edx < 64)

				targets_supported |= (1ULL << regs.edx);

			break;

		default:

			/* Unknown CPUID.PCONFIG subleaf: ignore */

			break;

		}

	}

out:

	return 0;

}

arch_initcall(intel_pconfig_init);