Commit 07993df5 authored by Matt Olson's avatar Matt Olson Committed by Jakub Kicinski
Browse files

gve: Update QPL page registration logic 



For DQO, change QPL page registration logic to be more flexible to honor
the "max_registered_pages" parameter from the gVNIC device.

Previously the number of RX pages per QPL was hardcoded to twice the
ring size, and the number of TX pages per QPL was dictated by the device
in the DQO-QPL device option. Now [in DQO-QPL mode], the driver will
ignore the "tx_pages_per_qpl" parameter indicated in the DQO-QPL device
option and instead allocate up to (tx_queue_length / 2) pages per TX QPL
and up to (rx_queue_length * 2) pages per RX QPL while keeping the total
number of pages under the "max_registered_pages".

Merge DQO and GQI QPL page calculation logic into a unified
gve_update_num_qpl_pages function. Add rx_pages_per_qpl to the priv
struct for consumption by both DQO and GQI.

Signed-off-by: default avatarMatt Olson <maolson@google.com>
Signed-off-by: default avatarMax Yuan <maxyuan@google.com>
Reviewed-by: default avatarJordan Rhee <jordanrhee@google.com>
Reviewed-by: default avatarHarshitha Ramamurthy <hramamurthy@google.com>
Reviewed-by: default avatarWillem de Bruijn <willemb@google.com>
Reviewed-by: default avatarPraveen Kaligineedi <pkaligineedi@google.com>
Signed-off-by: default avatarJoshua Washington <joshwash@google.com>
Link: https://patch.msgid.link/20260225182342.1049816-2-joshwash@google.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent a9a13c73

drivers/net/ethernet/google/gve/gve.h

+7 −11
Original line number Diff line number Diff line
@@ -79,8 +79,6 @@ 


#define GVE_DEFAULT_HEADER_BUFFER_SIZE 128



#define DQO_QPL_DEFAULT_TX_PAGES 512



/* Maximum TSO size supported on DQO */

#define GVE_DQO_TX_MAX	0x3FFFF
@@ -711,6 +709,7 @@ struct gve_ptype_lut { 
/* Parameters for allocating resources for tx queues */

struct gve_tx_alloc_rings_cfg {

	struct gve_tx_queue_config *qcfg;

	u16 pages_per_qpl;



	u16 num_xdp_rings;
@@ -726,6 +725,7 @@ struct gve_rx_alloc_rings_cfg { 
	/* tx config is also needed to determine QPL ids */

	struct gve_rx_queue_config *qcfg_rx;

	struct gve_tx_queue_config *qcfg_tx;

	u16 pages_per_qpl;



	u16 ring_size;

	u16 packet_buffer_size;
@@ -816,7 +816,8 @@ struct gve_priv { 
	u16 min_rx_desc_cnt;

	bool modify_ring_size_enabled;

	bool default_min_ring_size;

	u16 tx_pages_per_qpl; /* Suggested number of pages per qpl for TX queues by NIC */

	u16 tx_pages_per_qpl;

	u16 rx_pages_per_qpl;

	u64 max_registered_pages;

	u64 num_registered_pages; /* num pages registered with NIC */

	struct bpf_prog *xdp_prog; /* XDP BPF program */
@@ -1150,14 +1151,6 @@ static inline u32 gve_rx_start_qpl_id(const struct gve_tx_queue_config *tx_cfg) 
	return gve_get_rx_qpl_id(tx_cfg, 0);

}



static inline u32 gve_get_rx_pages_per_qpl_dqo(u32 rx_desc_cnt)

{

	/* For DQO, page count should be more than ring size for

	 * out-of-order completions. Set it to two times of ring size.

	 */

	return 2 * rx_desc_cnt;

}



/* Returns the correct dma direction for tx and rx qpls */

static inline enum dma_data_direction gve_qpl_dma_dir(struct gve_priv *priv,

						      int id)
@@ -1308,6 +1301,9 @@ int gve_reset(struct gve_priv *priv, bool attempt_teardown); 
void gve_get_curr_alloc_cfgs(struct gve_priv *priv,

			     struct gve_tx_alloc_rings_cfg *tx_alloc_cfg,

			     struct gve_rx_alloc_rings_cfg *rx_alloc_cfg);

void gve_update_num_qpl_pages(struct gve_priv *priv,

			      struct gve_rx_alloc_rings_cfg *rx_alloc_cfg,

			      struct gve_tx_alloc_rings_cfg *tx_alloc_cfg);

int gve_adjust_config(struct gve_priv *priv,

		      struct gve_tx_alloc_rings_cfg *tx_alloc_cfg,

		      struct gve_rx_alloc_rings_cfg *rx_alloc_cfg);

drivers/net/ethernet/google/gve/gve_adminq.c

+0 −8
Original line number Diff line number Diff line
@@ -970,14 +970,6 @@ static void gve_enable_supported_features(struct gve_priv *priv, 
		priv->dev->max_mtu = be16_to_cpu(dev_op_jumbo_frames->max_mtu);

	}



	/* Override pages for qpl for DQO-QPL */

	if (dev_op_dqo_qpl) {

		priv->tx_pages_per_qpl =

			be16_to_cpu(dev_op_dqo_qpl->tx_pages_per_qpl);

		if (priv->tx_pages_per_qpl == 0)

			priv->tx_pages_per_qpl = DQO_QPL_DEFAULT_TX_PAGES;

	}



	if (dev_op_buffer_sizes &&

	    (supported_features_mask & GVE_SUP_BUFFER_SIZES_MASK)) {

		priv->max_rx_buffer_size =

drivers/net/ethernet/google/gve/gve_buffer_mgmt_dqo.c

+1 −1
Original line number Diff line number Diff line
@@ -133,7 +133,7 @@ int gve_alloc_qpl_page_dqo(struct gve_rx_ring *rx, 
	u32 idx;



	idx = rx->dqo.next_qpl_page_idx;

	if (idx >= gve_get_rx_pages_per_qpl_dqo(priv->rx_desc_cnt)) {

	if (idx >= priv->rx_pages_per_qpl) {

		net_err_ratelimited("%s: Out of QPL pages\n",

				    priv->dev->name);

		return -ENOMEM;

drivers/net/ethernet/google/gve/gve_main.c

+41 −0
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ 
#include <linux/filter.h>

#include <linux/interrupt.h>

#include <linux/irq.h>

#include <linux/math64.h>

#include <linux/module.h>

#include <linux/pci.h>

#include <linux/sched.h>
@@ -966,6 +967,7 @@ static void gve_tx_get_curr_alloc_cfg(struct gve_priv *priv, 
	cfg->qcfg = &priv->tx_cfg;

	cfg->raw_addressing = !gve_is_qpl(priv);

	cfg->ring_size = priv->tx_desc_cnt;

	cfg->pages_per_qpl = priv->tx_pages_per_qpl;

	cfg->num_xdp_rings = cfg->qcfg->num_xdp_queues;

	cfg->tx = priv->tx;

}
@@ -997,12 +999,48 @@ static void gve_tx_start_rings(struct gve_priv *priv, int num_rings) 
	}

}



void gve_update_num_qpl_pages(struct gve_priv *priv,

			      struct gve_rx_alloc_rings_cfg *rx_alloc_cfg,

			      struct gve_tx_alloc_rings_cfg *tx_alloc_cfg)

{

	u64 ideal_tx_pages, ideal_rx_pages;

	u16 tx_num_queues, rx_num_queues;

	u64 max_pages, tx_pages;



	if (priv->queue_format == GVE_GQI_QPL_FORMAT) {

		rx_alloc_cfg->pages_per_qpl = rx_alloc_cfg->ring_size;

	} else if (priv->queue_format == GVE_DQO_QPL_FORMAT) {

		/*

		 * We want 2 pages per RX descriptor and half a page per TX

		 * descriptor, which means the fraction ideal_tx_pages /

		 * (ideal_tx_pages + ideal_rx_pages) of the pages we allocate

		 * should be for TX. Shrink proportionally as necessary to avoid

		 * allocating more than max_registered_pages total pages.

		 */

		tx_num_queues = tx_alloc_cfg->qcfg->num_queues;

		rx_num_queues = rx_alloc_cfg->qcfg_rx->num_queues;



		ideal_tx_pages = tx_alloc_cfg->ring_size * tx_num_queues / 2;

		ideal_rx_pages = rx_alloc_cfg->ring_size * rx_num_queues * 2;

		max_pages = min(priv->max_registered_pages,

				ideal_tx_pages + ideal_rx_pages);



		tx_pages = div64_u64(max_pages * ideal_tx_pages,

				     ideal_tx_pages + ideal_rx_pages);

		tx_alloc_cfg->pages_per_qpl = div_u64(tx_pages, tx_num_queues);

		rx_alloc_cfg->pages_per_qpl = div_u64(max_pages - tx_pages,

						      rx_num_queues);

	}

}



static int gve_queues_mem_alloc(struct gve_priv *priv,

				struct gve_tx_alloc_rings_cfg *tx_alloc_cfg,

				struct gve_rx_alloc_rings_cfg *rx_alloc_cfg)

{

	int err;



	gve_update_num_qpl_pages(priv, rx_alloc_cfg, tx_alloc_cfg);



	if (gve_is_gqi(priv))

		err = gve_tx_alloc_rings_gqi(priv, tx_alloc_cfg);

	else
@@ -1293,6 +1331,7 @@ static void gve_rx_get_curr_alloc_cfg(struct gve_priv *priv, 
	cfg->raw_addressing = !gve_is_qpl(priv);

	cfg->enable_header_split = priv->header_split_enabled;

	cfg->ring_size = priv->rx_desc_cnt;

	cfg->pages_per_qpl = priv->rx_pages_per_qpl;

	cfg->packet_buffer_size = priv->rx_cfg.packet_buffer_size;

	cfg->rx = priv->rx;

	cfg->xdp = !!cfg->qcfg_tx->num_xdp_queues;
@@ -1372,6 +1411,8 @@ static int gve_queues_start(struct gve_priv *priv, 
	priv->rx_cfg = *rx_alloc_cfg->qcfg_rx;

	priv->tx_desc_cnt = tx_alloc_cfg->ring_size;

	priv->rx_desc_cnt = rx_alloc_cfg->ring_size;

	priv->tx_pages_per_qpl = tx_alloc_cfg->pages_per_qpl;

	priv->rx_pages_per_qpl = rx_alloc_cfg->pages_per_qpl;



	gve_tx_start_rings(priv, gve_num_tx_queues(priv));

	gve_rx_start_rings(priv, rx_alloc_cfg->qcfg_rx->num_queues);

drivers/net/ethernet/google/gve/gve_rx.c

+1 −4
Original line number Diff line number Diff line
@@ -278,7 +278,6 @@ int gve_rx_alloc_ring_gqi(struct gve_priv *priv, 
	struct device *hdev = &priv->pdev->dev;

	u32 slots = cfg->ring_size;

	int filled_pages;

	int qpl_page_cnt;

	u32 qpl_id = 0;

	size_t bytes;

	int err;
@@ -314,10 +313,8 @@ int gve_rx_alloc_ring_gqi(struct gve_priv *priv, 


	if (!rx->data.raw_addressing) {

		qpl_id = gve_get_rx_qpl_id(cfg->qcfg_tx, rx->q_num);

		qpl_page_cnt = cfg->ring_size;



		rx->data.qpl = gve_alloc_queue_page_list(priv, qpl_id,

							 qpl_page_cnt);

							 cfg->pages_per_qpl);

		if (!rx->data.qpl) {

			err = -ENOMEM;

			goto abort_with_copy_pool;