Commit 07bfa9cd authored by Leo Ma's avatar Leo Ma Committed by Alex Deucher
Browse files

drm/amd/display: Add HDMI DSC native YCbCr422 support 



[WHY && HOW]
For some HDMI OVT timing, YCbCr422 encoding fails at the DSC
bandwidth check. The root cause is our DSC policy for timing
doesn't account for HDMI YCbCr422 native support.

Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Reviewed-by: default avatarChris Park <chris.park@amd.com>
Signed-off-by: default avatarLeo Ma <hanghong.ma@amd.com>
Signed-off-by: default avatarAlex Hung <alex.hung@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e79563bf

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

+2 −2
Original line number Diff line number Diff line
@@ -1147,7 +1147,7 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, 
		params[count].num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;

		params[count].bpp_overwrite = aconnector->dsc_settings.dsc_bits_per_pixel;

		params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported;

		dc_dsc_get_policy_for_timing(params[count].timing, 0, &dsc_policy);

		dc_dsc_get_policy_for_timing(params[count].timing, 0, &dsc_policy, dc_link_get_highest_encoding_format(stream->link));

		if (!dc_dsc_compute_bandwidth_range(

				stream->sink->ctx->dc->res_pool->dscs[0],

				stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
@@ -1681,7 +1681,7 @@ static bool is_dsc_common_config_possible(struct dc_stream_state *stream, 
{

	struct dc_dsc_policy dsc_policy = {0};



	dc_dsc_get_policy_for_timing(&stream->timing, 0, &dsc_policy);

	dc_dsc_get_policy_for_timing(&stream->timing, 0, &dsc_policy, dc_link_get_highest_encoding_format(stream->link));

	dc_dsc_compute_bandwidth_range(stream->sink->ctx->dc->res_pool->dscs[0],

				       stream->sink->ctx->dc->debug.dsc_min_slice_height_override,

				       dsc_policy.min_target_bpp * 16,

drivers/gpu/drm/amd/display/dc/dc_dsc.h

+2 −1
Original line number Diff line number Diff line
@@ -101,7 +101,8 @@ uint32_t dc_dsc_stream_bandwidth_overhead_in_kbps( 
 */

void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing,

		uint32_t max_target_bpp_limit_override_x16,

		struct dc_dsc_policy *policy);

		struct dc_dsc_policy *policy,

		const enum dc_link_encoding_format link_encoding);



void dc_dsc_policy_set_max_target_bpp_limit(uint32_t limit);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

+3 −2
Original line number Diff line number Diff line
@@ -883,7 +883,7 @@ static bool setup_dsc_config( 


	memset(dsc_cfg, 0, sizeof(struct dc_dsc_config));



	dc_dsc_get_policy_for_timing(timing, options->max_target_bpp_limit_override_x16, &policy);

	dc_dsc_get_policy_for_timing(timing, options->max_target_bpp_limit_override_x16, &policy, link_encoding);

	pic_width = timing->h_addressable + timing->h_border_left + timing->h_border_right;

	pic_height = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
@@ -1173,7 +1173,8 @@ uint32_t dc_dsc_stream_bandwidth_overhead_in_kbps( 


void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing,

		uint32_t max_target_bpp_limit_override_x16,

		struct dc_dsc_policy *policy)

		struct dc_dsc_policy *policy,

		const enum dc_link_encoding_format link_encoding)

{

	uint32_t bpc = 0;