Commit 07c34b37 authored by Bjorn Andersson's avatar Bjorn Andersson
Browse files

Merge branch '20230707035744.22245-2-quic_jkona@quicinc.com' into clk-for-6.7 

Merge the SM8550 camera clock controller patches through a topic branch,
to make them available for the DeviceTree source as well.
parents 1fa2d1a8 a209cf9c

Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml

+6 −2
Original line number Diff line number Diff line
@@ -13,11 +13,15 @@ description: | 
  Qualcomm camera clock control module provides the clocks, resets and power

  domains on SM8450.



  See also:: include/dt-bindings/clock/qcom,sm8450-camcc.h

  See also::

    include/dt-bindings/clock/qcom,sm8450-camcc.h

    include/dt-bindings/clock/qcom,sm8550-camcc.h



properties:

  compatible:

    const: qcom,sm8450-camcc

    enum:

      - qcom,sm8450-camcc

      - qcom,sm8550-camcc



  clocks:

    items:

drivers/clk/qcom/Kconfig

+7 −0
Original line number Diff line number Diff line
@@ -764,6 +764,13 @@ config SM_CAMCC_8450 
	  Support for the camera clock controller on SM8450 devices.

	  Say Y if you want to support camera devices and camera functionality.



config SM_CAMCC_8550

	tristate "SM8550 Camera Clock Controller"

	select SM_GCC_8550

	help

	  Support for the camera clock controller on SM8550 devices.

	  Say Y if you want to support camera devices and camera functionality.



config SM_DISPCC_6115

	tristate "SM6115 Display Clock Controller"

	depends on ARM64 || COMPILE_TEST

drivers/clk/qcom/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -102,6 +102,7 @@ obj-$(CONFIG_SDX_GCC_75) += gcc-sdx75.o 
obj-$(CONFIG_SM_CAMCC_6350) += camcc-sm6350.o

obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o

obj-$(CONFIG_SM_CAMCC_8450) += camcc-sm8450.o

obj-$(CONFIG_SM_CAMCC_8550) += camcc-sm8550.o

obj-$(CONFIG_SM_DISPCC_6115) += dispcc-sm6115.o

obj-$(CONFIG_SM_DISPCC_6125) += dispcc-sm6125.o

obj-$(CONFIG_SM_DISPCC_6350) += dispcc-sm6350.o

drivers/clk/qcom/camcc-sm8550.c

0 → 100644
+3564 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/clk/qcom/clk-alpha-pll.c

+29 −0
Original line number Diff line number Diff line
@@ -271,6 +271,7 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); 
#define LUCID_EVO_ENABLE_VOTE_RUN       BIT(25)

#define LUCID_EVO_PLL_L_VAL_MASK        GENMASK(15, 0)

#define LUCID_EVO_PLL_CAL_L_VAL_SHIFT	16

#define LUCID_OLE_PLL_RINGOSC_CAL_L_VAL_SHIFT	24



/* ZONDA PLL specific */

#define ZONDA_PLL_OUT_MASK	0xf
@@ -2119,6 +2120,34 @@ void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regma 
}

EXPORT_SYMBOL_GPL(clk_lucid_evo_pll_configure);



void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

				 const struct alpha_pll_config *config)

{

	u32 lval = config->l;



	lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT;

	lval |= TRION_PLL_CAL_VAL << LUCID_OLE_PLL_RINGOSC_CAL_L_VAL_SHIFT;

	clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval);

	clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);

	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);

	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);

	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);

	clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);

	clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);

	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);

	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);

	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);

	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val);



	/* Disable PLL output */

	regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);



	/* Set operation mode to STANDBY and de-assert the reset */

	regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);

	regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);

}

EXPORT_SYMBOL_GPL(clk_lucid_ole_pll_configure);



static int alpha_pll_lucid_evo_enable(struct clk_hw *hw)

{

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);