Unverified Commit 07df87c0 authored by Conor Dooley's avatar Conor Dooley Committed by Palmer Dabbelt
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dt-bindings: riscv: permit numbers in "riscv,isa" 



There are some extensions that contain numbers, such as Zve32f, which
are enabled by the "max" cpu type in QEMU.

Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
Acked-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20231208-uncolored-oxidant-5ab37dd3ab84@spud


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent a4528161

Documentation/devicetree/bindings/riscv/extensions.yaml

+1 −1
Original line number Diff line number Diff line
@@ -48,7 +48,7 @@ properties: 
      insensitive, letters in the riscv,isa string must be all

      lowercase.

    $ref: /schemas/types.yaml#/definitions/string

    pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$

    pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[0-9a-z])+)?(?:_[hsxz](?:[0-9a-z])+)*$

    deprecated: true



  riscv,isa-base: