Commit 080612b2 authored by Marc Zyngier's avatar Marc Zyngier
Browse files

Merge branch kvm-arm64/nv-timers into kvmarm-master/next 



* kvm-arm64/nv-timers:
  : .
  : Nested Virt support for the EL2 timers. From the initial cover letter:
  :
  : "Here's another batch of NV-related patches, this time bringing in most
  : of the timer support for EL2 as well as nested guests.
  :
  : The code is pretty convoluted for a bunch of reasons:
  :
  : - FEAT_NV2 breaks the timer semantics by redirecting HW controls to
  :   memory, meaning that a guest could setup a timer and never see it
  :   firing until the next exit
  :
  : - We go try hard to reflect the timer state in memory, but that's not
  :   great.
  :
  : - With FEAT_ECV, we can finally correctly emulate the virtual timer,
  :   but this emulation is pretty costly
  :
  : - As a way to make things suck less, we handle timer reads as early as
  :   possible, and only defer writes to the normal trap handling
  :
  : - Finally, some implementations are badly broken, and require some
  :   hand-holding, irrespective of NV support. So we try and reuse the NV
  :   infrastructure to make them usable. This could be further optimised,
  :   but I'm running out of patience for this sort of HW.
  :
  : [...]"
  : .
  KVM: arm64: nv: Fix doc header layout for timers
  KVM: arm64: nv: Document EL2 timer API
  KVM: arm64: Work around x1e's CNTVOFF_EL2 bogosity
  KVM: arm64: nv: Sanitise CNTHCTL_EL2
  KVM: arm64: nv: Propagate CNTHCTL_EL2.EL1NV{P,V}CT bits
  KVM: arm64: nv: Add trap routing for CNTHCTL_EL2.EL1{NVPCT,NVVCT,TVT,TVCT}
  KVM: arm64: Handle counter access early in non-HYP context
  KVM: arm64: nv: Accelerate EL0 counter accesses from hypervisor context
  KVM: arm64: nv: Accelerate EL0 timer read accesses when FEAT_ECV in use
  KVM: arm64: nv: Use FEAT_ECV to trap access to EL0 timers
  KVM: arm64: nv: Publish emulated timer interrupt state in the in-memory state
  KVM: arm64: nv: Sync nested timer state with FEAT_NV2
  KVM: arm64: nv: Add handling of EL2-specific timer registers

Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parents e880b16e 54478636

Documentation/virt/kvm/devices/vcpu.rst

+8 −6
Original line number Diff line number Diff line
@@ -142,8 +142,8 @@ the cpu field to the processor id. 


:Architectures: ARM64



2.1. ATTRIBUTES: KVM_ARM_VCPU_TIMER_IRQ_VTIMER, KVM_ARM_VCPU_TIMER_IRQ_PTIMER

-----------------------------------------------------------------------------

2.1. ATTRIBUTES: KVM_ARM_VCPU_TIMER_IRQ_{VTIMER,PTIMER,HVTIMER,HPTIMER}

-----------------------------------------------------------------------



:Parameters: in kvm_device_attr.addr the address for the timer interrupt is a

	     pointer to an int
@@ -159,10 +159,12 @@ A value describing the architected timer interrupt number when connected to an 
in-kernel virtual GIC.  These must be a PPI (16 <= intid < 32).  Setting the

attribute overrides the default values (see below).



=============================  ==========================================

==============================  ==========================================

KVM_ARM_VCPU_TIMER_IRQ_VTIMER   The EL1 virtual timer intid (default: 27)

KVM_ARM_VCPU_TIMER_IRQ_PTIMER   The EL1 physical timer intid (default: 30)

=============================  ==========================================

KVM_ARM_VCPU_TIMER_IRQ_HVTIMER  The EL2 virtual timer intid (default: 28)

KVM_ARM_VCPU_TIMER_IRQ_HPTIMER  The EL2 physical timer intid (default: 26)

==============================  ==========================================



Setting the same PPI for different timers will prevent the VCPUs from running.

Setting the interrupt number on a VCPU configures all VCPUs created at that

arch/arm64/include/asm/cputype.h

+2 −0
Original line number Diff line number Diff line
@@ -122,6 +122,7 @@ 
#define QCOM_CPU_PART_KRYO_3XX_SILVER	0x803

#define QCOM_CPU_PART_KRYO_4XX_GOLD	0x804

#define QCOM_CPU_PART_KRYO_4XX_SILVER	0x805

#define QCOM_CPU_PART_ORYON_X1		0x001



#define NVIDIA_CPU_PART_DENVER		0x003

#define NVIDIA_CPU_PART_CARMEL		0x004
@@ -198,6 +199,7 @@ 
#define MIDR_QCOM_KRYO_3XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_3XX_SILVER)

#define MIDR_QCOM_KRYO_4XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_GOLD)

#define MIDR_QCOM_KRYO_4XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_SILVER)

#define MIDR_QCOM_ORYON_X1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_ORYON_X1)

#define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)

#define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)

#define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)

arch/arm64/include/asm/kvm_host.h

+1 −1
Original line number Diff line number Diff line
@@ -493,7 +493,6 @@ enum vcpu_sysreg { 
	VBAR_EL2,	/* Vector Base Address Register (EL2) */

	RVBAR_EL2,	/* Reset Vector Base Address Register */

	CONTEXTIDR_EL2,	/* Context ID Register (EL2) */

	CNTHCTL_EL2,	/* Counter-timer Hypervisor Control register */

	SP_EL2,		/* EL2 Stack Pointer */

	CNTHP_CTL_EL2,

	CNTHP_CVAL_EL2,
@@ -504,6 +503,7 @@ enum vcpu_sysreg { 
	MARKER(__SANITISED_REG_START__),

	TCR2_EL2,	/* Extended Translation Control Register (EL2) */

	MDCR_EL2,	/* Monitor Debug Configuration Register (EL2) */

	CNTHCTL_EL2,	/* Counter-timer Hypervisor Control register */



	/* Any VNCR-capable reg goes after this point */

	MARKER(__VNCR_START__),

arch/arm64/include/asm/sysreg.h

+4 −0
Original line number Diff line number Diff line
@@ -477,6 +477,7 @@ 
#define SYS_CNTFRQ_EL0			sys_reg(3, 3, 14, 0, 0)



#define SYS_CNTPCT_EL0			sys_reg(3, 3, 14, 0, 1)

#define SYS_CNTVCT_EL0			sys_reg(3, 3, 14, 0, 2)

#define SYS_CNTPCTSS_EL0		sys_reg(3, 3, 14, 0, 5)

#define SYS_CNTVCTSS_EL0		sys_reg(3, 3, 14, 0, 6)
@@ -484,14 +485,17 @@ 
#define SYS_CNTP_CTL_EL0		sys_reg(3, 3, 14, 2, 1)

#define SYS_CNTP_CVAL_EL0		sys_reg(3, 3, 14, 2, 2)



#define SYS_CNTV_TVAL_EL0		sys_reg(3, 3, 14, 3, 0)

#define SYS_CNTV_CTL_EL0		sys_reg(3, 3, 14, 3, 1)

#define SYS_CNTV_CVAL_EL0		sys_reg(3, 3, 14, 3, 2)



#define SYS_AARCH32_CNTP_TVAL		sys_reg(0, 0, 14, 2, 0)

#define SYS_AARCH32_CNTP_CTL		sys_reg(0, 0, 14, 2, 1)

#define SYS_AARCH32_CNTPCT		sys_reg(0, 0, 0, 14, 0)

#define SYS_AARCH32_CNTVCT		sys_reg(0, 1, 0, 14, 0)

#define SYS_AARCH32_CNTP_CVAL		sys_reg(0, 2, 0, 14, 0)

#define SYS_AARCH32_CNTPCTSS		sys_reg(0, 8, 0, 14, 0)

#define SYS_AARCH32_CNTVCTSS		sys_reg(0, 9, 0, 14, 0)



#define __PMEV_op2(n)			((n) & 0x7)

#define __CNTR_CRm(n)			(0x8 | (((n) >> 3) & 0x3))

arch/arm64/kernel/cpu_errata.c

+8 −0
Original line number Diff line number Diff line
@@ -786,6 +786,14 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		ERRATA_MIDR_RANGE_LIST(erratum_ac03_cpu_38_list),

	},

#endif

	{

		.desc = "Broken CNTVOFF_EL2",

		.capability = ARM64_WORKAROUND_QCOM_ORYON_CNTVOFF,

		ERRATA_MIDR_RANGE_LIST(((const struct midr_range[]) {

					MIDR_ALL_VERSIONS(MIDR_QCOM_ORYON_X1),

					{}

				})),

	},

	{

	}

};