Commit 080950cb authored by Karthi Kandasamy's avatar Karthi Kandasamy Committed by Alex Deucher
Browse files

drm/amd/display: Update dc_tiling_info union to structure 



[WHY]
The `dc_tiling_info` union previously did not have a field to
specify the active GFX format, assuming only one format would
be used per DCN version. from DCN4+, support for switching
between different GFX formats is introduced, requiring a way
to track which format is currently in use.

[HOW]
Updated the `dc_tiling_info` union to include a new field that
explicitly indicates the currently used GFX format.
This allows the system to determine the active GFX format
and take the correct programming path accordingly.

[Description]
The union `dc_tiling_info` has been updated to support multiple
GFX formats by adding a new field for identifying the active format.
This update ensures that the correct programming path is followed
based on the selected format. All references to `dc_tiling_info`
in the codebase have been updated to reflect the new structure.

Reviewed-by: default avatarAlvin Lee <alvin.lee2@amd.com>
Signed-off-by: default avatarKarthi Kandasamy <karthi.kandasamy@amd.com>
Signed-off-by: default avatarRoman Li <roman.li@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e8b19ffe

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

+7 −7
Original line number Diff line number Diff line
@@ -177,7 +177,7 @@ static unsigned int amdgpu_dm_plane_modifier_gfx9_swizzle_mode(uint64_t modifier 
	return AMD_FMT_MOD_GET(TILE, modifier);

}



static void amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(union dc_tiling_info *tiling_info,

static void amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(struct dc_tiling_info *tiling_info,

							     uint64_t tiling_flags)

{

	/* Fill GFX8 params */
@@ -210,7 +210,7 @@ static void amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(union dc_tiling_inf 
}



static void amdgpu_dm_plane_fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev,

							      union dc_tiling_info *tiling_info)

							      struct dc_tiling_info *tiling_info)

{

	/* Fill GFX9 params */

	tiling_info->gfx9.num_pipes =
@@ -231,7 +231,7 @@ static void amdgpu_dm_plane_fill_gfx9_tiling_info_from_device(const struct amdgp 
}



static void amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier(const struct amdgpu_device *adev,

								union dc_tiling_info *tiling_info,

								struct dc_tiling_info *tiling_info,

								uint64_t modifier)

{

	unsigned int mod_bank_xor_bits = AMD_FMT_MOD_GET(BANK_XOR_BITS, modifier);
@@ -261,7 +261,7 @@ static void amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier(const struct amd 
static int amdgpu_dm_plane_validate_dcc(struct amdgpu_device *adev,

					const enum surface_pixel_format format,

					const enum dc_rotation_angle rotation,

					const union dc_tiling_info *tiling_info,

					const struct dc_tiling_info *tiling_info,

					const struct dc_plane_dcc_param *dcc,

					const struct dc_plane_address *address,

					const struct plane_size *plane_size)
@@ -308,7 +308,7 @@ static int amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers(struct amdg 
								     const enum surface_pixel_format format,

								     const enum dc_rotation_angle rotation,

								     const struct plane_size *plane_size,

								     union dc_tiling_info *tiling_info,

								     struct dc_tiling_info *tiling_info,

								     struct dc_plane_dcc_param *dcc,

								     struct dc_plane_address *address)

{
@@ -358,7 +358,7 @@ static int amdgpu_dm_plane_fill_gfx12_plane_attributes_from_modifiers(struct amd 
								      const enum surface_pixel_format format,

								      const enum dc_rotation_angle rotation,

								      const struct plane_size *plane_size,

								      union dc_tiling_info *tiling_info,

								      struct dc_tiling_info *tiling_info,

								      struct dc_plane_dcc_param *dcc,

								      struct dc_plane_address *address)

{
@@ -834,7 +834,7 @@ int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev, 
			     const enum surface_pixel_format format,

			     const enum dc_rotation_angle rotation,

			     const uint64_t tiling_flags,

			     union dc_tiling_info *tiling_info,

			     struct dc_tiling_info *tiling_info,

			     struct plane_size *plane_size,

			     struct dc_plane_dcc_param *dcc,

			     struct dc_plane_address *address,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h

+1 −1
Original line number Diff line number Diff line
@@ -47,7 +47,7 @@ int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev, 
				 const enum surface_pixel_format format,

				 const enum dc_rotation_angle rotation,

				 const uint64_t tiling_flags,

				 union dc_tiling_info *tiling_info,

				 struct dc_tiling_info *tiling_info,

				 struct plane_size *plane_size,

				 struct dc_plane_dcc_param *dcc,

				 struct dc_plane_address *address,

drivers/gpu/drm/amd/display/dc/core/dc.c

+1 −1
Original line number Diff line number Diff line
@@ -2555,7 +2555,7 @@ static enum surface_update_type get_plane_info_update_type(const struct dc *dc, 




	if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info,

			sizeof(union dc_tiling_info)) != 0) {

			sizeof(struct dc_tiling_info)) != 0) {

		update_flags->bits.swizzle_change = 1;

		elevate_update_type(&update_type, UPDATE_TYPE_MED);

drivers/gpu/drm/amd/display/dc/dc.h

+2 −2
Original line number Diff line number Diff line
@@ -1306,7 +1306,7 @@ struct dc_plane_state { 
	struct rect clip_rect;



	struct plane_size plane_size;

	union dc_tiling_info tiling_info;

	struct dc_tiling_info tiling_info;



	struct dc_plane_dcc_param dcc;
@@ -1377,7 +1377,7 @@ struct dc_plane_state { 


struct dc_plane_info {

	struct plane_size plane_size;

	union dc_tiling_info tiling_info;

	struct dc_tiling_info tiling_info;

	struct dc_plane_dcc_param dcc;

	enum surface_pixel_format format;

	enum dc_rotation_angle rotation;

drivers/gpu/drm/amd/display/dc/dc_hw_types.h

+94 −82
Original line number Diff line number Diff line
@@ -341,8 +341,19 @@ enum swizzle_mode_addr3_values { 
	DC_ADDR3_SW_UNKNOWN = DC_ADDR3_SW_MAX

};



union dc_tiling_info {



enum dc_gfxversion {

	DcGfxVersion7 = 0,

	DcGfxVersion8,

	DcGfxVersion9,

	DcGfxVersion10,

	DcGfxVersion11,

	DcGfxAddr3,

	DcGfxVersionUnknown

};



 struct dc_tiling_info {

	unsigned int gfxversion;     // Specifies which part of the union to use. Must use DalGfxVersion enum

	union {

		struct {

			/* Specifies the number of memory banks for tiling

			 *	purposes.
@@ -425,6 +436,7 @@ union dc_tiling_info { 
			enum swizzle_mode_addr3_values swizzle;

		} gfx_addr3;/*gfx with addr3 and above*/

	};

};



/* Rotation angle */

enum dc_rotation_angle {