Commit 0809d9b0 authored by Vitaly Kuznetsov's avatar Vitaly Kuznetsov Committed by Paolo Bonzini
Browse files

KVM: VMX: Cache MSR_IA32_VMX_MISC in vmcs_config 



Like other host VMX control MSRs, MSR_IA32_VMX_MISC can be cached in
vmcs_config to avoid the need to re-read it later, e.g. from
cpu_has_vmx_intel_pt() or cpu_has_vmx_shadow_vmcs().

No (real) functional change intended.

Reviewed-by: default avatarJim Mattson <jmattson@google.com>
Reviewed-by: default avatarMaxim Levitsky <mlevitsk@redhat.com>
Signed-off-by: default avatarVitaly Kuznetsov <vkuznets@redhat.com>
Signed-off-by: default avatarSean Christopherson <seanjc@google.com>
Link: https://lore.kernel.org/r/20220830133737.1539624-33-vkuznets@redhat.com


Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent bcdf201f

arch/x86/kvm/vmx/capabilities.h

+3 −8
Original line number Diff line number Diff line
@@ -65,6 +65,7 @@ struct vmcs_config { 
	u64 cpu_based_3rd_exec_ctrl;

	u32 vmexit_ctrl;

	u32 vmentry_ctrl;

	u64 misc;

	struct nested_vmx_msrs nested;

};

extern struct vmcs_config vmcs_config;
@@ -225,11 +226,8 @@ static inline bool cpu_has_vmx_vmfunc(void) 


static inline bool cpu_has_vmx_shadow_vmcs(void)

{

	u64 vmx_msr;



	/* check if the cpu supports writing r/o exit information fields */

	rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);

	if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))

	if (!(vmcs_config.misc & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))

		return false;



	return vmcs_config.cpu_based_2nd_exec_ctrl &
@@ -371,10 +369,7 @@ static inline bool cpu_has_vmx_invvpid_global(void) 


static inline bool cpu_has_vmx_intel_pt(void)

{

	u64 vmx_msr;



	rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);

	return (vmx_msr & MSR_IA32_VMX_MISC_INTEL_PT) &&

	return (vmcs_config.misc & MSR_IA32_VMX_MISC_INTEL_PT) &&

		(vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_PT_USE_GPA) &&

		(vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_RTIT_CTL);

}

arch/x86/kvm/vmx/vmx.c

+5 −3
Original line number Diff line number Diff line
@@ -2555,6 +2555,7 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf, 
	u64 _cpu_based_3rd_exec_control = 0;

	u32 _vmexit_control = 0;

	u32 _vmentry_control = 0;

	u64 misc_msr;

	int i;



	/*
@@ -2688,6 +2689,8 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf, 
	if (((vmx_msr_high >> 18) & 15) != 6)

		return -EIO;



	rdmsrl(MSR_IA32_VMX_MISC, misc_msr);



	vmcs_conf->size = vmx_msr_high & 0x1fff;

	vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
@@ -2699,6 +2702,7 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf, 
	vmcs_conf->cpu_based_3rd_exec_ctrl = _cpu_based_3rd_exec_control;

	vmcs_conf->vmexit_ctrl         = _vmexit_control;

	vmcs_conf->vmentry_ctrl        = _vmentry_control;

	vmcs_conf->misc	= misc_msr;



	return 0;

}
@@ -8315,11 +8319,9 @@ static __init int hardware_setup(void) 


	if (enable_preemption_timer) {

		u64 use_timer_freq = 5000ULL * 1000 * 1000;

		u64 vmx_msr;



		rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);

		cpu_preemption_timer_multi =

			vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;

			vmcs_config.misc & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;



		if (tsc_khz)

			use_timer_freq = (u64)tsc_khz * 1000;