Commit 0843e0ce authored by Marc Zyngier's avatar Marc Zyngier Committed by Oliver Upton
Browse files

KVM: arm64: Get rid of ARM64_FEATURE_MASK() 



The ARM64_FEATURE_MASK() macro was a hack introduce whilst the
automatic generation of sysreg encoding was introduced, and was
too unreliable to be entirely trusted.

We are in a better place now, and we could really do without this
macro. Get rid of it altogether.

Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20250817202158.395078-7-maz@kernel.org


Signed-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
parent 7a765aa8

arch/arm64/include/asm/sysreg.h

+0 −3
Original line number Diff line number Diff line
@@ -1146,9 +1146,6 @@ 


#define ARM64_FEATURE_FIELD_BITS	4



/* Defined for compatibility only, do not add new users. */

#define ARM64_FEATURE_MASK(x)	(x##_MASK)



#ifdef __ASSEMBLY__



	.macro	mrs_s, rt, sreg

arch/arm64/kvm/arm.c

+4 −4
Original line number Diff line number Diff line
@@ -2404,12 +2404,12 @@ static u64 get_hyp_id_aa64pfr0_el1(void) 
	 */

	u64 val = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);



	val &= ~(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2) |

		 ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3));

	val &= ~(ID_AA64PFR0_EL1_CSV2 |

		 ID_AA64PFR0_EL1_CSV3);



	val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2),

	val |= FIELD_PREP(ID_AA64PFR0_EL1_CSV2,

			  arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED);

	val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3),

	val |= FIELD_PREP(ID_AA64PFR0_EL1_CSV3,

			  arm64_get_meltdown_state() == SPECTRE_UNAFFECTED);



	return val;

arch/arm64/kvm/sys_regs.c

+20 −20
Original line number Diff line number Diff line
@@ -1615,18 +1615,18 @@ static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu, 
		break;

	case SYS_ID_AA64ISAR1_EL1:

		if (!vcpu_has_ptrauth(vcpu))

			val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) |

				 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) |

				 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) |

				 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI));

			val &= ~(ID_AA64ISAR1_EL1_APA |

				 ID_AA64ISAR1_EL1_API |

				 ID_AA64ISAR1_EL1_GPA |

				 ID_AA64ISAR1_EL1_GPI);

		break;

	case SYS_ID_AA64ISAR2_EL1:

		if (!vcpu_has_ptrauth(vcpu))

			val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) |

				 ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3));

			val &= ~(ID_AA64ISAR2_EL1_APA3 |

				 ID_AA64ISAR2_EL1_GPA3);

		if (!cpus_have_final_cap(ARM64_HAS_WFXT) ||

		    has_broken_cntvoff())

			val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT);

			val &= ~ID_AA64ISAR2_EL1_WFxT;

		break;

	case SYS_ID_AA64ISAR3_EL1:

		val &= ID_AA64ISAR3_EL1_FPRCVT | ID_AA64ISAR3_EL1_FAMINMAX;
@@ -1642,7 +1642,7 @@ static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu, 
		       ID_AA64MMFR3_EL1_S1PIE;

		break;

	case SYS_ID_MMFR4_EL1:

		val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX);

		val &= ~ID_MMFR4_EL1_CCIDX;

		break;

	}
@@ -1828,22 +1828,22 @@ static u64 sanitise_id_aa64pfr1_el1(const struct kvm_vcpu *vcpu, u64 val) 
	u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);



	if (!kvm_has_mte(vcpu->kvm)) {

		val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE);

		val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE_frac);

		val &= ~ID_AA64PFR1_EL1_MTE;

		val &= ~ID_AA64PFR1_EL1_MTE_frac;

	}



	if (!(cpus_have_final_cap(ARM64_HAS_RASV1P1_EXTN) &&

	      SYS_FIELD_GET(ID_AA64PFR0_EL1, RAS, pfr0) == ID_AA64PFR0_EL1_RAS_IMP))

		val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_RAS_frac);



	val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME);

	val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_RNDR_trap);

	val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_NMI);

	val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_GCS);

	val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_THE);

	val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTEX);

	val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_PFAR);

	val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MPAM_frac);

		val &= ~ID_AA64PFR1_EL1_RAS_frac;



	val &= ~ID_AA64PFR1_EL1_SME;

	val &= ~ID_AA64PFR1_EL1_RNDR_trap;

	val &= ~ID_AA64PFR1_EL1_NMI;

	val &= ~ID_AA64PFR1_EL1_GCS;

	val &= ~ID_AA64PFR1_EL1_THE;

	val &= ~ID_AA64PFR1_EL1_MTEX;

	val &= ~ID_AA64PFR1_EL1_PFAR;

	val &= ~ID_AA64PFR1_EL1_MPAM_frac;



	return val;

}

tools/arch/arm64/include/asm/sysreg.h

+0 −3
Original line number Diff line number Diff line
@@ -1080,9 +1080,6 @@ 


#define ARM64_FEATURE_FIELD_BITS	4



/* Defined for compatibility only, do not add new users. */

#define ARM64_FEATURE_MASK(x)	(x##_MASK)



#ifdef __ASSEMBLY__



	.macro	mrs_s, rt, sreg

tools/testing/selftests/kvm/arm64/aarch32_id_regs.c

+1 −1
Original line number Diff line number Diff line
@@ -146,7 +146,7 @@ static bool vcpu_aarch64_only(struct kvm_vcpu *vcpu) 


	val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1));



	el0 = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0), val);

	el0 = FIELD_GET(ID_AA64PFR0_EL1_EL0, val);

	return el0 == ID_AA64PFR0_EL1_EL0_IMP;

}