Commit 08448812 authored by Nicholas Kazlauskas's avatar Nicholas Kazlauskas Committed by Alex Deucher
Browse files

drm/amd/display: Remove min_dst_y_next_start check for Z8 



[Why]
Flickering occurs on DRR supported panels when engaged in DRR due to
min_dst_y_next becoming larger than the frame size itself.

[How]
In general, we should be able to enter Z8 when this is engaged but it
might be a net power loss even if the calculation wasn't bugged.

Don't support enabling Z8 during the DRR region.

Cc: stable@vger.kernel.org # 6.1+
Reviewed-by: default avatarSyed Hassan <syed.hassan@amd.com>
Acked-by: default avatarHamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6b0b7789

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

+1 −14
Original line number Diff line number Diff line
@@ -950,10 +950,8 @@ static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struc 
{

	int plane_count;

	int i;

	unsigned int min_dst_y_next_start_us;



	plane_count = 0;

	min_dst_y_next_start_us = 0;

	for (i = 0; i < dc->res_pool->pipe_count; i++) {

		if (context->res_ctx.pipe_ctx[i].plane_state)

			plane_count++;
@@ -975,26 +973,15 @@ static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struc 
	else if (context->stream_count == 1 &&  context->streams[0]->signal == SIGNAL_TYPE_EDP) {

		struct dc_link *link = context->streams[0]->sink->link;

		struct dc_stream_status *stream_status = &context->stream_status[0];

		struct dc_stream_state *current_stream = context->streams[0];

		int minmum_z8_residency = dc->debug.minimum_z8_residency_time > 0 ? dc->debug.minimum_z8_residency_time : 1000;

		bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency;

		bool is_pwrseq0 = link->link_index == 0;

		bool isFreesyncVideo;



		isFreesyncVideo = current_stream->adjust.v_total_min == current_stream->adjust.v_total_max;

		isFreesyncVideo = isFreesyncVideo && current_stream->timing.v_total < current_stream->adjust.v_total_min;

		for (i = 0; i < dc->res_pool->pipe_count; i++) {

			if (context->res_ctx.pipe_ctx[i].stream == current_stream && isFreesyncVideo) {

				min_dst_y_next_start_us = context->res_ctx.pipe_ctx[i].dlg_regs.min_dst_y_next_start_us;

				break;

			}

		}



		/* Don't support multi-plane configurations */

		if (stream_status->plane_count > 1)

			return DCN_ZSTATE_SUPPORT_DISALLOW;



		if (is_pwrseq0 && (context->bw_ctx.dml.vba.StutterPeriod > 5000.0 || min_dst_y_next_start_us > 5000))

		if (is_pwrseq0 && context->bw_ctx.dml.vba.StutterPeriod > 5000.0)

			return DCN_ZSTATE_SUPPORT_ALLOW;

		else if (is_pwrseq0 && link->psr_settings.psr_version == DC_PSR_VERSION_1 && !link->panel_config.psr.disable_psr)

			return allow_z8 ? DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY : DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY;