Commit 084a55b2 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/gvt: remove the unused end parameter from calc_index() 



All callers of calc_index() pass 0 for the end parameter. Remove it.

Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi Wang <zhi.wang.linux@gmail.com>
Cc: intel-gvt-dev@lists.freedesktop.org
Reviewed-by: default avatarZhi Wang <zhiwang@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/aaa24a5cbcf876d3b95e0f5f6594f972a860b6bc.1717773890.git.jani.nikula@intel.com


Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent d6bbb6e5

drivers/gpu/drm/i915/gvt/handlers.c

+8 −9
Original line number Diff line number Diff line
@@ -881,12 +881,11 @@ static int check_fdi_rx_train_status(struct intel_vgpu *vgpu, 
#define INVALID_INDEX (~0U)



static unsigned int calc_index(unsigned int offset, unsigned int start,

	unsigned int next, unsigned int end, i915_reg_t i915_end)

			       unsigned int next, i915_reg_t _end)

{

	u32 end = i915_mmio_reg_offset(_end);

	unsigned int range = next - start;



	if (!end)

		end = i915_mmio_reg_offset(i915_end);

	if (offset < start || offset > end)

		return INVALID_INDEX;

	offset -= start;
@@ -894,13 +893,13 @@ static unsigned int calc_index(unsigned int offset, unsigned int start, 
}



#define FDI_RX_CTL_TO_PIPE(offset) \

	calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C))

	calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, FDI_RX_CTL(PIPE_C))



#define FDI_TX_CTL_TO_PIPE(offset) \

	calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C))

	calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, FDI_TX_CTL(PIPE_C))



#define FDI_RX_IMR_TO_PIPE(offset) \

	calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C))

	calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, FDI_RX_IMR(PIPE_C))



static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu,

		unsigned int offset, void *p_data, unsigned int bytes)
@@ -944,7 +943,7 @@ static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu, 
}



#define DP_TP_CTL_TO_PORT(offset) \

	calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E))

	calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, DP_TP_CTL(PORT_E))



static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,

		void *p_data, unsigned int bytes)
@@ -1008,7 +1007,7 @@ static int south_chicken2_mmio_write(struct intel_vgpu *vgpu, 
}



#define DSPSURF_TO_PIPE(offset) \

	calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(dev_priv, PIPE_C))

	calc_index(offset, _DSPASURF, _DSPBSURF, DSPSURF(dev_priv, PIPE_C))



static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,

		void *p_data, unsigned int bytes)
@@ -1031,7 +1030,7 @@ static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 
}



#define SPRSURF_TO_PIPE(offset) \

	calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C))

	calc_index(offset, _SPRA_SURF, _SPRB_SURF, SPRSURF(PIPE_C))



static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,

		void *p_data, unsigned int bytes)