Commit 086502e9 authored by Georgi Djakov's avatar Georgi Djakov
Browse files

Merge branch 'icc-mahua' into icc-next 

Mahua is a derivative of the Glymur SoC and shares a significant
portion of its interconnect topology with Glymur. As such, this
series extends the existing Glymur interconnect driver to support
Mahua, reusing common definitions where possible and adding
SoC-specific configurations where necessary.

* icc-mahua
  dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Mahua SoC
  interconnect: qcom: glymur: Add Mahua SoC support

Link: https://msgid.link/20260209-mahua_icc-v3-0-c65f3dfd72c8@oss.qualcomm.com


Signed-off-by: default avatarGeorgi Djakov <djakov@kernel.org>
parents b6adc224 dfff14a4

Documentation/devicetree/bindings/interconnect/qcom,glymur-rpmh.yaml

+111 −25
Original line number Diff line number Diff line
@@ -4,7 +4,7 @@ 
$id: http://devicetree.org/schemas/interconnect/qcom,glymur-rpmh.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm RPMh Network-On-Chip Interconnect on Glymur SoC

title: Qualcomm RPMh Network-On-Chip Interconnect on Glymur and Mahua SoCs



maintainers:

  - Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
@@ -21,7 +21,72 @@ description: | 


properties:

  compatible:

    enum:

    oneOf:

      - items:

          - enum:

              - qcom,mahua-aggre1-noc

          - const: qcom,glymur-aggre1-noc

      - items:

          - enum:

              - qcom,mahua-aggre2-noc

          - const: qcom,glymur-aggre2-noc

      - items:

          - enum:

              - qcom,mahua-aggre3-noc

          - const: qcom,glymur-aggre3-noc

      - items:

          - enum:

              - qcom,mahua-aggre4-noc

          - const: qcom,glymur-aggre4-noc

      - items:

          - enum:

              - qcom,mahua-clk-virt

          - const: qcom,glymur-clk-virt

      - items:

          - enum:

              - qcom,mahua-cnoc-main

          - const: qcom,glymur-cnoc-main

      - items:

          - enum:

              - qcom,mahua-lpass-ag-noc

          - const: qcom,glymur-lpass-ag-noc

      - items:

          - enum:

              - qcom,mahua-lpass-lpiaon-noc

          - const: qcom,glymur-lpass-lpiaon-noc

      - items:

          - enum:

              - qcom,mahua-lpass-lpicx-noc

          - const: qcom,glymur-lpass-lpicx-noc

      - items:

          - enum:

              - qcom,mahua-mmss-noc

          - const: qcom,glymur-mmss-noc

      - items:

          - enum:

              - qcom,mahua-nsinoc

          - const: qcom,glymur-nsinoc

      - items:

          - enum:

              - qcom,mahua-nsp-noc

          - const: qcom,glymur-nsp-noc

      - items:

          - enum:

              - qcom,mahua-oobm-ss-noc

          - const: qcom,glymur-oobm-ss-noc

      - items:

          - enum:

              - qcom,mahua-pcie-east-anoc

          - const: qcom,glymur-pcie-east-anoc

      - items:

          - enum:

              - qcom,mahua-pcie-east-slv-noc

          - const: qcom,glymur-pcie-east-slv-noc

      - items:

          - enum:

              - qcom,mahua-system-noc

          - const: qcom,glymur-system-noc

      - enum:

          - qcom,glymur-aggre1-noc

          - qcom,glymur-aggre2-noc

          - qcom,glymur-aggre3-noc
@@ -43,6 +108,11 @@ properties: 
          - qcom,glymur-pcie-west-anoc

          - qcom,glymur-pcie-west-slv-noc

          - qcom,glymur-system-noc

          - qcom,mahua-cnoc-cfg

          - qcom,mahua-hscnoc

          - qcom,mahua-mc-virt

          - qcom,mahua-pcie-west-anoc

          - qcom,mahua-pcie-west-slv-noc



  reg:

    maxItems: 1
@@ -63,6 +133,7 @@ allOf: 
            enum:

              - qcom,glymur-clk-virt

              - qcom,glymur-mc-virt

              - qcom,mahua-mc-virt

    then:

      properties:

        reg: false
@@ -85,6 +156,20 @@ allOf: 
            - description: aggre PCIE_4 WEST AXI clock

            - description: aggre PCIE_6 WEST AXI clock



  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,mahua-pcie-west-anoc

    then:

      properties:

        clocks:

          items:

            - description: aggre PCIE_3B WEST AXI clock

            - description: aggre PCIE_4 WEST AXI clock

            - description: aggre PCIE_6 WEST AXI clock



  - if:

      properties:

        compatible:
@@ -131,10 +216,11 @@ allOf: 
        compatible:

          contains:

            enum:

              - qcom,glymur-pcie-west-anoc

              - qcom,glymur-pcie-east-anoc

              - qcom,glymur-aggre2-noc

              - qcom,glymur-aggre4-noc

              - qcom,glymur-pcie-east-anoc

              - qcom,glymur-pcie-west-anoc

              - qcom,mahua-pcie-west-anoc

    then:

      required:

        - clocks

drivers/interconnect/qcom/glymur.c

+33 −5
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
#include <linux/interconnect-provider.h>

#include <linux/module.h>

#include <linux/of_platform.h>

#include <linux/property.h>

#include <dt-bindings/interconnect/qcom,glymur-rpmh.h>



#include "bcm-voter.h"
@@ -1985,7 +1986,7 @@ static struct qcom_icc_bcm * const cnoc_cfg_bcms[] = { 
	&bcm_cn1,

};



static struct qcom_icc_node * const cnoc_cfg_nodes[] = {

static struct qcom_icc_node *cnoc_cfg_nodes[] = {

	[MASTER_CNOC_CFG] = &qsm_cfg,

	[SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,

	[SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
@@ -2093,7 +2094,7 @@ static struct qcom_icc_bcm * const hscnoc_bcms[] = { 
	&bcm_sh1,

};



static struct qcom_icc_node * const hscnoc_nodes[] = {

static struct qcom_icc_node *hscnoc_nodes[] = {

	[MASTER_GPU_TCU] = &alm_gpu_tcu,

	[MASTER_PCIE_TCU] = &alm_pcie_qtc,

	[MASTER_SYS_TCU] = &alm_sys_tcu,
@@ -2377,7 +2378,7 @@ static struct qcom_icc_bcm * const pcie_west_anoc_bcms[] = { 
	&bcm_sn6,

};



static struct qcom_icc_node * const pcie_west_anoc_nodes[] = {

static struct qcom_icc_node *pcie_west_anoc_nodes[] = {

	[MASTER_PCIE_WEST_ANOC_CFG] = &qsm_pcie_west_anoc_cfg,

	[MASTER_PCIE_2] = &xm_pcie_2,

	[MASTER_PCIE_3A] = &xm_pcie_3a,
@@ -2409,7 +2410,7 @@ static struct qcom_icc_bcm * const pcie_west_slv_noc_bcms[] = { 
	&bcm_sn6,

};



static struct qcom_icc_node * const pcie_west_slv_noc_nodes[] = {

static struct qcom_icc_node *pcie_west_slv_noc_nodes[] = {

	[MASTER_HSCNOC_PCIE_WEST] = &qnm_hscnoc_pcie_west,

	[MASTER_CNOC_PCIE_WEST_SLAVE_CFG] = &qsm_cnoc_pcie_west_slave_cfg,

	[SLAVE_HSCNOC_PCIE_WEST_MS_MPU_CFG] = &qhs_hscnoc_pcie_west_ms_mpu_cfg,
@@ -2470,6 +2471,28 @@ static const struct qcom_icc_desc glymur_system_noc = { 
	.num_bcms = ARRAY_SIZE(system_noc_bcms),

};



static int glymur_qnoc_probe(struct platform_device *pdev)

{

	if (device_is_compatible(&pdev->dev, "qcom,mahua-mc-virt")) {

		llcc_mc.channels = 8;

		ebi.channels = 8;

	} else if (device_is_compatible(&pdev->dev, "qcom,mahua-hscnoc")) {

		qns_llcc.channels = 8;

		chm_apps.channels = 4;

		qnm_pcie_west.buswidth = 32;

		hscnoc_nodes[MASTER_WLAN_Q6] = NULL;

	} else if (device_is_compatible(&pdev->dev, "qcom,mahua-pcie-west-anoc")) {

		qns_pcie_west_mem_noc.buswidth = 32;

		pcie_west_anoc_nodes[MASTER_PCIE_3A] = NULL;

	} else if (device_is_compatible(&pdev->dev, "qcom,mahua-cnoc-cfg")) {

		cnoc_cfg_nodes[SLAVE_PCIE_3A_CFG] = NULL;

	} else if (device_is_compatible(&pdev->dev, "qcom,mahua-pcie-west-slv-noc")) {

		pcie_west_slv_noc_nodes[SLAVE_PCIE_3A] = NULL;

	}



	return qcom_icc_rpmh_probe(pdev);

}



static const struct of_device_id qnoc_of_match[] = {

	{ .compatible = "qcom,glymur-aggre1-noc", .data = &glymur_aggre1_noc},

	{ .compatible = "qcom,glymur-aggre2-noc", .data = &glymur_aggre2_noc},
@@ -2477,12 +2500,15 @@ static const struct of_device_id qnoc_of_match[] = { 
	{ .compatible = "qcom,glymur-aggre4-noc", .data = &glymur_aggre4_noc},

	{ .compatible = "qcom,glymur-clk-virt", .data = &glymur_clk_virt},

	{ .compatible = "qcom,glymur-cnoc-cfg", .data = &glymur_cnoc_cfg},

	{ .compatible = "qcom,mahua-cnoc-cfg", .data = &glymur_cnoc_cfg},

	{ .compatible = "qcom,glymur-cnoc-main", .data = &glymur_cnoc_main},

	{ .compatible = "qcom,glymur-hscnoc", .data = &glymur_hscnoc},

	{ .compatible = "qcom,mahua-hscnoc", .data = &glymur_hscnoc},

	{ .compatible = "qcom,glymur-lpass-ag-noc", .data = &glymur_lpass_ag_noc},

	{ .compatible = "qcom,glymur-lpass-lpiaon-noc", .data = &glymur_lpass_lpiaon_noc},

	{ .compatible = "qcom,glymur-lpass-lpicx-noc", .data = &glymur_lpass_lpicx_noc},

	{ .compatible = "qcom,glymur-mc-virt", .data = &glymur_mc_virt},

	{ .compatible = "qcom,mahua-mc-virt", .data = &glymur_mc_virt},

	{ .compatible = "qcom,glymur-mmss-noc", .data = &glymur_mmss_noc},

	{ .compatible = "qcom,glymur-nsinoc", .data = &glymur_nsinoc},

	{ .compatible = "qcom,glymur-nsp-noc", .data = &glymur_nsp_noc},
@@ -2490,14 +2516,16 @@ static const struct of_device_id qnoc_of_match[] = { 
	{ .compatible = "qcom,glymur-pcie-east-anoc", .data = &glymur_pcie_east_anoc},

	{ .compatible = "qcom,glymur-pcie-east-slv-noc", .data = &glymur_pcie_east_slv_noc},

	{ .compatible = "qcom,glymur-pcie-west-anoc", .data = &glymur_pcie_west_anoc},

	{ .compatible = "qcom,mahua-pcie-west-anoc", .data = &glymur_pcie_west_anoc},

	{ .compatible = "qcom,glymur-pcie-west-slv-noc", .data = &glymur_pcie_west_slv_noc},

	{ .compatible = "qcom,mahua-pcie-west-slv-noc", .data = &glymur_pcie_west_slv_noc},

	{ .compatible = "qcom,glymur-system-noc", .data = &glymur_system_noc},

	{ }

};

MODULE_DEVICE_TABLE(of, qnoc_of_match);



static struct platform_driver qnoc_driver = {

	.probe = qcom_icc_rpmh_probe,

	.probe = glymur_qnoc_probe,

	.remove = qcom_icc_rpmh_remove,

	.driver = {

		.name = "qnoc-glymur",