Commit 088de129 authored by Swapnil Jakhade's avatar Swapnil Jakhade Committed by Vinod Koul
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dt-bindings: phy: cadence-torrent: Add optional input reference clock for PLL1 



Add a new optional input reference clock (pll1_refclk) for PLL1.
Update bindings to support dual reference clock multilink configurations.

Signed-off-by: default avatarSwapnil Jakhade <sjakhade@cadence.com>
Acked-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: default avatarRoger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20240104133013.2911035-2-sjakhade@cadence.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 2668cae8

Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml

+7 −3
Original line number Diff line number Diff line
@@ -35,14 +35,18 @@ properties: 
    minItems: 1

    maxItems: 2

    description:

      PHY reference clock for 1 item. Must contain an entry in clock-names.

      Optional Parent to enable output reference clock.

      PHY input reference clocks - refclk (for PLL0) & pll1_refclk (for PLL1).

      pll1_refclk is optional and used for multi-protocol configurations requiring

      separate reference clock for each protocol.

      Same refclk is used for both PLL0 and PLL1 if no separate pll1_refclk is used.

      Optional parent clock (phy_en_refclk) to enable a reference clock output feature

      on some platforms to output either derived or received reference clock.



  clock-names:

    minItems: 1

    items:

      - const: refclk

      - const: phy_en_refclk

      - enum: [ pll1_refclk, phy_en_refclk ]



  reg:

    minItems: 1