Commit 08de7f9d authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull MTD updates from Miquel Raynal:
 "MTD changes:

   - There's been no major core change, just a bunch of driver related
     improvements.

     Amongst them the conversion to of_property_present() for
     non-boolean properties, the addition of the support for Fujitsu
     MB85RS128TY FRAM, a couple of improvements to the phram driver and
     the usual load of misc changes.

  Raw NAND changes:

   - A new controller driver, from Nuvoton, has been merged

   - Bastien Curutchet has contributed a series improving the Davinci
     controller driver, both on the organization of the code, but also
     on the performance side. The binding has also been converted to
     yaml, received a new OOB layout and now supports on-die ECC engines

   - The Qualcomm controller driver has been deeply cleaned to extract
     some parts of the code into a shared file with the Qualcomm SPI
     memory controller

   - Aside from these main changes, the Cadence binding has been
     converted to yaml, the brcmnand controller driver has received a
     small fix, otherwise some more minor changes have also made their
     way in

  SPI NAND changes:

   - The SPI NAND subsystem has seen a great improvement, with the
     advent of DTR operations (DDR operations, which may be extended to
     the address cycles). The first vendor driver to benefit from these
     improvements is the Winbond driver

   - A new manufacturer driver is added SkyHigh, with a new constraint
     for the core, it is impossible to disable the on-die ECC engine

   - A Foresee device is also now supported

  SPI NOR changes:

   - Several flash entries have been added: Atmel AT25SF321, Spansion
     S28HL256T and S28HL02GT

   - Support for vcc-supply regulators and their DT bindings has been
     added

   - The mx25u25635f entry has been dropped. The flash shares its ID
     with mx25u25645g and both parts have an SFDP table. Removing their
     entry lets them be driven by the generic SFDP-based driver"

* tag 'mtd/for-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (47 commits)
  mtd: spinand: skyhigh: Align with recent read from cache variant changes
  mtd: spinand: winbond: Add support for DTR operations
  mtd: spinand: winbond: Add comment about naming
  mtd: spinand: winbond: Update the *JW chip definitions
  mtd: spinand: Add support for read DTR operations
  mtd: spinand: Enhance the logic when picking a variant
  mtd: spinand: Add an optional frequency to read from cache macros
  mtd: spinand: Create distinct fast and slow read from cache variants
  mtd: hyperbus: Use of_property_present() for non-boolean properties
  mtd: st_spi_fsm: Switch from CONFIG_PM_SLEEP guards to pm_sleep_ptr()
  mtd: rawnand: davinci: add ROM supported OOB layout
  mtd: spi-nor: sysfs: constify 'struct bin_attribute'
  mtd: spi-nor: spansion: Add support for S28HL02GT
  mtd: spi-nor: spansion: Add support for S28HL256T
  mtd: spi-nor: extend description of size member of struct flash_info
  mtd: rawnand: davinci: Reduce polling interval in NAND_OP_WAITRDY_INSTR
  mtd: rawnand: qcom: Fix build issue on x86 architecture
  mtd: rawnand: qcom: use FIELD_PREP and GENMASK
  mtd: nand: Add qpic_common API file
  mtd: rawnand: qcom: Add qcom prefix to common api
  ...
parents 647d6960 0ddeb4fe
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* Cadence NAND controller

Required properties:
  - compatible : "cdns,hp-nfc"
  - reg : Contains two entries, each of which is a tuple consisting of a
	  physical address and length. The first entry is the address and
	  length of the controller register set. The second entry is the
	  address and length of the Slave DMA data port.
  - reg-names: should contain "reg" and "sdma"
  - #address-cells: should be 1. The cell encodes the chip select connection.
  - #size-cells : should be 0.
  - interrupts : The interrupt number.
  - clocks: phandle of the controller core clock (nf_clk).

Optional properties:
  - dmas: shall reference DMA channel associated to the NAND controller
  - cdns,board-delay-ps : Estimated Board delay. The value includes the total
    round trip delay for the signals and is used for deciding on values
    associated with data read capture. The example formula for SDR mode is
    the following:
    board delay = RE#PAD delay + PCB trace to device + PCB trace from device
    + DQ PAD delay

Child nodes represent the available NAND chips.

Required properties of NAND chips:
  - reg: shall contain the native Chip Select ids from 0 to max supported by
    the cadence nand flash controller

See Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on
generic bindings.

Example:

nand_controller: nand-controller@60000000 {
	  compatible = "cdns,hp-nfc";
	  #address-cells = <1>;
	  #size-cells = <0>;
	  reg = <0x60000000 0x10000>, <0x80000000 0x10000>;
	  reg-names = "reg", "sdma";
	  clocks = <&nf_clk>;
	  cdns,board-delay-ps = <4830>;
	  interrupts = <2 0>;
	  nand@0 {
	      reg = <0>;
	      label = "nand-1";
	  };
	  nand@1 {
	      reg = <1>;
	      label = "nand-2";
	  };

};
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/cdns,hp-nfc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Cadence NAND controller

maintainers:
  - Niravkumar L Rabara <niravkumar.l.rabara@intel.com>

allOf:
  - $ref: nand-controller.yaml

properties:
  compatible:
    items:
      - const: cdns,hp-nfc

  reg:
    items:
      - description: Controller register set
      - description: Slave DMA data port register set

  reg-names:
    items:
      - const: reg
      - const: sdma

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  dmas:
    maxItems: 1

  cdns,board-delay-ps:
    description: |
      Estimated Board delay. The value includes the total round trip
      delay for the signals and is used for deciding on values associated
      with data read capture. The example formula for SDR mode is the
      following.
      board delay = RE#PAD delay + PCB trace to device + PCB trace from device
      + DQ PAD delay

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - clocks

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    nand-controller@10b80000 {
        compatible = "cdns,hp-nfc";
        reg = <0x10b80000 0x10000>,
              <0x10840000 0x10000>;
        reg-names = "reg", "sdma";
        #address-cells = <1>;
        #size-cells = <0>;
        interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&nf_clk>;
        cdns,board-delay-ps = <4830>;

        nand@0 {
            reg = <0>;
        };
    };
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Device tree bindings for Texas instruments Davinci/Keystone NAND controller

This file provides information, what the device node for the davinci/keystone
NAND interface contains.

Documentation:
Davinci DM646x - https://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
Kestone - https://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf

Required properties:

- compatible:			"ti,davinci-nand"
				"ti,keystone-nand"

- reg:				Contains 2 offset/length values:
				- offset and length for the access window.
				- offset and length for accessing the AEMIF
				control registers.

- ti,davinci-chipselect:	number of chipselect. Indicates on the
				davinci_nand driver which chipselect is used
				for accessing the nand.
				Can be in the range [0-3].

Recommended properties :

- ti,davinci-mask-ale:		mask for ALE. Needed for executing address
				phase. These offset will be added to the base
				address for the chip select space the NAND Flash
				device is connected to.
				If not set equal to 0x08.

- ti,davinci-mask-cle:		mask for CLE. Needed for executing command
				phase. These offset will be added to the base
				address for the chip select space the NAND Flash
				device is connected to.
				If not set equal to 0x10.

- ti,davinci-mask-chipsel:	mask for chipselect address. Needed to mask
				addresses for given chipselect.

- nand-ecc-mode:		operation mode of the NAND ecc mode. ECC mode
				valid values for davinci driver:
				- "none"
				- "soft"
				- "hw"

- ti,davinci-ecc-bits:		used ECC bits, currently supported 1 or 4.

- nand-bus-width:		buswidth 8 or 16. If not present 8.

- nand-on-flash-bbt:		use flash based bad block table support. OOB
				identifier is saved in OOB area. If not present
				false.

Deprecated properties:

- ti,davinci-ecc-mode:		operation mode of the NAND ecc mode. ECC mode
				valid values for davinci driver:
				- "none"
				- "soft"
				- "hw"

- ti,davinci-nand-buswidth:	buswidth 8 or 16. If not present 8.

- ti,davinci-nand-use-bbt:	use flash based bad block table support. OOB
				identifier is saved in OOB area. If not present
				false.

Nand device bindings may contain additional sub-nodes describing partitions of
the address space. See mtd.yaml for more detail. The NAND Flash timing
values must be programmed in the chip select’s node of AEMIF
memory-controller (see Documentation/devicetree/bindings/memory-controllers/
davinci-aemif.txt).

Example(da850 EVM ):

nand_cs3@62000000 {
	compatible = "ti,davinci-nand";
	reg = <0x62000000 0x807ff
	       0x68000000 0x8000>;
	ti,davinci-chipselect = <1>;
	ti,davinci-mask-ale = <0>;
	ti,davinci-mask-cle = <0>;
	ti,davinci-mask-chipsel = <0>;
	nand-ecc-mode = "hw";
	ti,davinci-ecc-bits = <4>;
	nand-on-flash-bbt;

	partition@180000 {
		label = "ubifs";
		reg = <0x180000 0x7e80000>;
	};
};
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@@ -96,6 +96,10 @@ properties:
      If "broken-flash-reset" is present then having this property does not
      make any difference.

  vcc-supply:
    description:
      Supply for the SPI NOR power.

  spi-cpol: true
  spi-cpha: true

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@@ -16,8 +16,9 @@ description: |

properties:
  compatible:
    items:
      - const: microchip,48l640
    enum:
      - fujitsu,mb85rs128ty
      - microchip,48l640

  reg:
    maxItems: 1
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