Commit 08f3e087 authored by James Clark's avatar James Clark Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor-events: Fix all remaining invalid JSON files 



Remove trailing commas. A later commit will make the parser more strict
and these will not be valid anymore.

Reviewed-by: default avatarAndi Kleen <ak@linux.intel.com>
Reviewed-by: default avatarJohn Garry <john.garry@huawei.com>
Reviewed-by: default avatarKajol <Jain&lt;kjain@linux.ibm.com>
Signed-off-by: default avatarJames Clark <james.clark@arm.com>
Acked-by: default avatarJiri Olsa <jolsa@redhat.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andrew.Kilroy@arm.com
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Nick.Forrington@arm.com
Cc: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lore.kernel.org/r/20211007110543.564963-2-james.clark@arm.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent c6c00900

tools/perf/pmu-events/arch/arm64/ampere/emag/bus.json

+1 −1
Original line number Diff line number Diff line
@@ -18,6 +18,6 @@ 
        "ArchStdEvent": "BUS_ACCESS_PERIPH"

    },

    {

        "ArchStdEvent": "BUS_ACCESS",

        "ArchStdEvent": "BUS_ACCESS"

    }

]

tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json

+10 −10
Original line number Diff line number Diff line
@@ -39,31 +39,31 @@ 
        "ArchStdEvent": "L2D_CACHE_INVAL"

    },

    {

        "ArchStdEvent": "L1I_CACHE_REFILL",

        "ArchStdEvent": "L1I_CACHE_REFILL"

    },

    {

        "ArchStdEvent": "L1I_TLB_REFILL",

        "ArchStdEvent": "L1I_TLB_REFILL"

    },

    {

        "ArchStdEvent": "L1D_CACHE_REFILL",

        "ArchStdEvent": "L1D_CACHE_REFILL"

    },

    {

        "ArchStdEvent": "L1D_CACHE",

        "ArchStdEvent": "L1D_CACHE"

    },

    {

        "ArchStdEvent": "L1D_TLB_REFILL",

        "ArchStdEvent": "L1D_TLB_REFILL"

    },

    {

        "ArchStdEvent": "L1I_CACHE",

        "ArchStdEvent": "L1I_CACHE"

    },

    {

        "ArchStdEvent": "L2D_CACHE",

        "ArchStdEvent": "L2D_CACHE"

    },

    {

        "ArchStdEvent": "L2D_CACHE_REFILL",

        "ArchStdEvent": "L2D_CACHE_REFILL"

    },

    {

        "ArchStdEvent": "L2D_CACHE_WB",

        "ArchStdEvent": "L2D_CACHE_WB"

    },

    {

        "PublicDescription": "This event counts any load or store operation which accesses the data L1 TLB",
@@ -72,7 +72,7 @@ 
    },

    {

        "PublicDescription": "This event counts any instruction fetch which accesses the instruction L1 TLB",

        "ArchStdEvent": "L1I_TLB",

        "ArchStdEvent": "L1I_TLB"

    },

    {

        "PublicDescription": "Level 2 access to data TLB that caused a page table walk. This event counts on any data access which causes L2D_TLB_REFILL to count",

tools/perf/pmu-events/arch/arm64/ampere/emag/clock.json

+1 −1
Original line number Diff line number Diff line 
[

    {

        "PublicDescription": "The number of core clock cycles",

        "ArchStdEvent": "CPU_CYCLES",

        "ArchStdEvent": "CPU_CYCLES"

    },

    {

        "PublicDescription": "FSU clocking gated off cycle",

tools/perf/pmu-events/arch/arm64/ampere/emag/exception.json

+2 −2
Original line number Diff line number Diff line
@@ -36,9 +36,9 @@ 
        "ArchStdEvent": "EXC_TRAP_FIQ"

    },

    {

        "ArchStdEvent": "EXC_TAKEN",

        "ArchStdEvent": "EXC_TAKEN"

    },

    {

        "ArchStdEvent": "EXC_RETURN",

        "ArchStdEvent": "EXC_RETURN"

    }

]

tools/perf/pmu-events/arch/arm64/ampere/emag/instruction.json

+5 −5
Original line number Diff line number Diff line
@@ -44,25 +44,25 @@ 
        "BriefDescription": "Software increment"

    },

    {

        "ArchStdEvent": "INST_RETIRED",

        "ArchStdEvent": "INST_RETIRED"

    },

    {

        "ArchStdEvent": "CID_WRITE_RETIRED",

        "BriefDescription": "Write to CONTEXTIDR"

    },

    {

        "ArchStdEvent": "INST_SPEC",

        "ArchStdEvent": "INST_SPEC"

    },

    {

        "ArchStdEvent": "TTBR_WRITE_RETIRED",

        "ArchStdEvent": "TTBR_WRITE_RETIRED"

    },

    {

        "PublicDescription": "This event counts all branches, taken or not. This excludes exception entries, debug entries and CCFAIL branches",

        "ArchStdEvent": "BR_RETIRED",

        "ArchStdEvent": "BR_RETIRED"

    },

    {

        "PublicDescription": "This event counts any branch counted by BR_RETIRED which is not correctly predicted and causes a pipeline flush",

        "ArchStdEvent": "BR_MIS_PRED_RETIRED",

        "ArchStdEvent": "BR_MIS_PRED_RETIRED"

    },

    {

        "PublicDescription": "Operation speculatively executed, NOP",