Commit 091b2eca authored by Paolo Bonzini's avatar Paolo Bonzini
Browse files

Merge tag 'kvmarm-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD 

KVM/arm64 updates for 6.12

* New features:

  - Add a Stage-2 page table dumper, reusing the main ptdump
    infrastructure, and allowing easier debugging of the our
    page-table infrastructure

  - Add FP8 support to the KVM/arm64 floating point handling.

  - Add NV support for the AT family of instructions, which mostly
    results in adding a page table walker that deals with most of the
    complexity of the architecture.

* Improvements, fixes and cleanups:

  - Add selftest checks for a bunch of timer emulation corner cases

  - Fix the multiple of cases where KVM/arm64 doesn't correctly handle
    the guest trying to use a GICv3 that isn't advertised

  - Remove REG_HIDDEN_USER from the sysreg infrastructure, making
    things little more simple

  - Prevent MTE tags being restored by userspace if we are actively
    logging writes, as that's a recipe for disaster

  - Correct the refcount on a page that is not considered for MTE tag
    copying (such as a device)

  - Relax the synchronisation when walking a page table to split block
    mappings, moving it at the end the walk, as there is no need to
    perform it on every store.

  - Fix boundary check when transfering memory using FFA

  - Fix pKVM TLB invalidation, only affecting currently out of tree
    code but worth addressing for peace of mind
parents 15e1c3d6 17a00056

Documentation/ABI/testing/sysfs-devices-system-cpu

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@@ -562,7 +562,8 @@ Description: Control Symmetric Multi Threading (SMT) 
			 ================ =========================================



			 If control status is "forceoff" or "notsupported" writes

			 are rejected.

			 are rejected. Note that enabling SMT on PowerPC skips

			 offline cores.



What:		/sys/devices/system/cpu/cpuX/power/energy_perf_bias

Date:		March 2019

Documentation/admin-guide/device-mapper/dm-crypt.rst

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@@ -162,6 +162,7 @@ iv_large_sectors 




Module parameters::



   max_read_size

   max_write_size

      Maximum size of read or write requests. When a request larger than this size

Documentation/arch/riscv/hwprobe.rst

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@@ -239,25 +239,33 @@ The following keys are defined: 
       ratified in commit 98918c844281 ("Merge pull request #1217 from

       riscv/zawrs") of riscv-isa-manual.



* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance

  information about the selected set of processors.

* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated.  Returns similar values to

     :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was

     mistakenly classified as a bitmask rather than a value.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNKNOWN`: The performance of misaligned

    accesses is unknown.

* :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`: An enum value describing

  the performance of misaligned scalar native word accesses on the selected set

  of processors.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_EMULATED`: Misaligned accesses are

    emulated via software, either in or below the kernel.  These accesses are

    always extremely slow.

  * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN`: The performance of

    misaligned scalar accesses is unknown.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_SLOW`: Misaligned accesses are slower

    than equivalent byte accesses.  Misaligned accesses may be supported

    directly in hardware, or trapped and emulated by software.

  * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED`: Misaligned scalar

    accesses are emulated via software, either in or below the kernel.  These

    accesses are always extremely slow.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_FAST`: Misaligned accesses are faster

    than equivalent byte accesses.

  * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW`: Misaligned scalar native

    word sized accesses are slower than the equivalent quantity of byte

    accesses. Misaligned accesses may be supported directly in hardware, or

    trapped and emulated by software.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNSUPPORTED`: Misaligned accesses are

    not supported at all and will generate a misaligned address fault.

  * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_FAST`: Misaligned scalar native

    word sized accesses are faster than the equivalent quantity of byte

    accesses.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED`: Misaligned scalar

    accesses are not supported at all and will generate a misaligned address

    fault.



* :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which

  represents the size of the Zicboz block in bytes.

Documentation/core-api/workqueue.rst

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@@ -260,7 +260,7 @@ Some users depend on strict execution ordering where only one work item 
is in flight at any given time and the work items are processed in

queueing order. While the combination of ``@max_active`` of 1 and

``WQ_UNBOUND`` used to achieve this behavior, this is no longer the

case. Use ``alloc_ordered_queue()`` instead.

case. Use alloc_ordered_workqueue() instead.





Example Execution Scenarios

Documentation/devicetree/bindings/clock/qcom,dispcc-sm6350.yaml

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@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# 
title: Qualcomm Display Clock & Reset Controller on SM6350



maintainers:

  - Konrad Dybcio <konrad.dybcio@somainline.org>

  - Konrad Dybcio <konradybcio@kernel.org>



description: |

  Qualcomm display clock control module provides the clocks, resets and power