Commit 0937c6e7 authored by Raag Jadav's avatar Raag Jadav Committed by Andi Shyti
Browse files

drm/i915/dg2: Implement Wa_14022698537 



G8 power state entry is disabled due to a limitation on DG2, so we
enable it from driver with Wa_14022698537. For now we enable it for
all DG2 devices with the exception of a few, for which, we enable
only when paired with whitelisted CPU models. This works with native
ASPM and reduces idle power consumption.

$ echo powersave > /sys/module/pcie_aspm/parameters/policy
$ lspci -s 0000:03:00.0 -vvv
LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk-

v2: Fix Wa_ID and include it in subject (Badal)
    Rephrase commit message (Jani)
v3: Move workaround to i915_pcode_init() (Badal, Anshuman)
    Re-order macro (Riana)
v4: Spell fix (Riana)

Signed-off-by: default avatarRaag Jadav <raag.jadav@intel.com>
Acked-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarRiana Tauro <riana.tauro@intel.com>
Reviewed-by: default avatarAndi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: default avatarAndi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241211115952.1659287-5-raag.jadav@intel.com
parent d58db10e

drivers/gpu/drm/i915/i915_driver.c

+15 −0
Original line number Diff line number Diff line
@@ -95,11 +95,13 @@ 
#include "i915_memcpy.h"

#include "i915_perf.h"

#include "i915_query.h"

#include "i915_reg.h"

#include "i915_switcheroo.h"

#include "i915_sysfs.h"

#include "i915_utils.h"

#include "i915_vgpu.h"

#include "intel_clock_gating.h"

#include "intel_cpu_info.h"

#include "intel_gvt.h"

#include "intel_memory_region.h"

#include "intel_pci_config.h"
@@ -424,6 +426,18 @@ static int i915_set_dma_info(struct drm_i915_private *i915) 
	return ret;

}



/* Wa_14022698537:dg2 */

static void i915_enable_g8(struct drm_i915_private *i915)

{

	if (IS_DG2(i915)) {

		if (IS_DG2_D(i915) && !intel_match_g8_cpu())

			return;



		snb_pcode_write_p(&i915->uncore, PCODE_POWER_SETUP,

				  POWER_SETUP_SUBCOMMAND_G8_ENABLE, 0, 0);

	}

}



static int i915_pcode_init(struct drm_i915_private *i915)

{

	struct intel_gt *gt;
@@ -437,6 +451,7 @@ static int i915_pcode_init(struct drm_i915_private *i915) 
		}

	}



	i915_enable_g8(i915);

	return 0;

}

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -3578,6 +3578,7 @@ 
#define	    POWER_SETUP_I1_WATTS		REG_BIT(31)

#define	    POWER_SETUP_I1_SHIFT		6	/* 10.6 fixed point format */

#define	    POWER_SETUP_I1_DATA_MASK		REG_GENMASK(15, 0)

#define     POWER_SETUP_SUBCOMMAND_G8_ENABLE	0x6

#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23

#define   XEHP_PCODE_FREQUENCY_CONFIG		0x6e	/* pvc */

/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */