dt-bindings: PCI: Convert marvell,armada8k-pcie to schema

# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/marvell,armada8k-pcie.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Marvell Armada 7K/8K PCIe interface

maintainers:

  - Thomas Petazzoni <thomas.petazzoni@bootlin.com>

description:

  This PCIe host controller is based on the Synopsys DesignWare PCIe IP.

select:

  properties:

    compatible:

      contains:

        enum:

          - marvell,armada8k-pcie

  required:

    - compatible

allOf:

  - $ref: snps,dw-pcie.yaml#

properties:

  compatible:

    items:

      - enum:

          - marvell,armada8k-pcie

      - const: snps,dw-pcie

  reg:

    maxItems: 2

  reg-names:

    items:

      - const: ctrl

      - const: config

  clocks:

    minItems: 1

    maxItems: 2

  clock-names:

    items:

      - const: core

      - const: reg

  interrupts:

    maxItems: 1

  msi-parent:

    maxItems: 1

  phys:

    minItems: 1

    maxItems: 4

  phy-names:

    minItems: 1

    maxItems: 4

  marvell,reset-gpio:

    maxItems: 1

    deprecated: true

required:

  - interrupt-map

  - clocks

  - msi-parent

unevaluatedProperties: false

examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/interrupt-controller/irq.h>

    pcie@f2600000 {

        compatible = "marvell,armada8k-pcie", "snps,dw-pcie";

        reg = <0xf2600000 0x10000>, <0xf6f00000 0x80000>;

        reg-names = "ctrl", "config";

        #address-cells = <3>;

        #size-cells = <2>;

        #interrupt-cells = <1>;

        device_type = "pci";

        dma-coherent;

        msi-parent = <&gic_v2m0>;

        ranges = <0x81000000 0 0xf9000000 0xf9000000 0 0x10000>,  /* downstream I/O */

                 <0x82000000 0 0xf6000000 0xf6000000 0 0xf00000>;  /* non-prefetchable memory */

        interrupt-map-mask = <0 0 0 0>;

        interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;

        interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;

        num-lanes = <1>;

        clocks = <&cpm_syscon0 1 13>;

    };

...

* Marvell Armada 7K/8K PCIe interface

This PCIe host controller is based on the Synopsys DesignWare PCIe IP

and thus inherits all the common properties defined in snps,dw-pcie.yaml.

Required properties:

- compatible: "marvell,armada8k-pcie"

- reg: must contain two register regions

   - the control register region

   - the config space region

- reg-names:

   - "ctrl" for the control register region

   - "config" for the config space region

- interrupts: Interrupt specifier for the PCIe controller

- clocks: reference to the PCIe controller clocks

- clock-names: mandatory if there is a second clock, in this case the

   name must be "core" for the first clock and "reg" for the second

   one

Optional properties:

- phys: phandle(s) to PHY node(s) following the generic PHY bindings.

	Either 1, 2 or 4 PHYs might be needed depending on the number of

	PCIe lanes.

- phy-names: names of the PHYs corresponding to the number of lanes.

	Must be "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy" for

	2 PHYs.

Example:

	pcie@f2600000 {

		compatible = "marvell,armada8k-pcie", "snps,dw-pcie";

		reg = <0 0xf2600000 0 0x10000>, <0 0xf6f00000 0 0x80000>;

		reg-names = "ctrl", "config";

		#address-cells = <3>;

		#size-cells = <2>;

		#interrupt-cells = <1>;

		device_type = "pci";

		dma-coherent;

		bus-range = <0 0xff>;

		ranges = <0x81000000 0 0xf9000000 0  0xf9000000 0 0x10000	/* downstream I/O */

			  0x82000000 0 0xf6000000 0  0xf6000000 0 0xf00000>;	/* non-prefetchable memory */

		interrupt-map-mask = <0 0 0 0>;

		interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;

		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;

		num-lanes = <1>;

		clocks = <&cpm_syscon0 1 13>;

	};

            above for new bindings.

          oneOf:

            - description: See native 'dbi' clock for details

              enum: [ pcie, pcie_apb_sys, aclk_dbi ]

              enum: [ pcie, pcie_apb_sys, aclk_dbi, reg ]

            - description: See native 'mstr/slv' clock for details

              enum: [ pcie_bus, pcie_inbound_axi, pcie_aclk, aclk_mst, aclk_slv ]

            - description: See native 'pipe' clock for details

          oneOf:

            - pattern: '^pcie(-?phy[0-9]*)?$'

            - pattern: '^p2u-[0-7]$'

            - pattern: '^cp[01]-pcie[0-2]-x[124](-lane[0-3])?-phy$'  # marvell,armada8k-pcie

  reset-gpio:

    deprecated: true

            Vendor-specific CSR names. Consider using the generic names above

            for new bindings.

          oneOf:

            - description: See native 'dbi' CSR region for details.

              enum: [ ctrl ]

            - description: See native 'elbi/app' CSR region for details.

              enum: [ apb, mgmt, link, ulreg, appl ]

            - description: See native 'atu' CSR region for details.

              const: slcr

    allOf:

      - contains:

          const: dbi

          enum: [ dbi, ctrl ]

      - contains:

          const: config

L:	linux-pci@vger.kernel.org

L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)

S:	Maintained

F:	Documentation/devicetree/bindings/pci/pci-armada8k.txt

F:	Documentation/devicetree/bindings/pci/marvell,armada8k-pcie.yaml

F:	drivers/pci/controller/dwc/pcie-armada8k.c

PCI DRIVER FOR CADENCE PCIE IP