Commit 0975c4de authored by Austin Zheng's avatar Austin Zheng Committed by Alex Deucher
Browse files

drm/amd/display: DML2.1 Reintegration 



[Summary of changes]
- Updated structs
- Renaming of variables for clarity

Reviewed-by: default avatarDillon Varone <dillon.varone@amd.com>
Signed-off-by: default avatarAustin Zheng <Austin.Zheng@amd.com>
Signed-off-by: default avatarRoman Li <roman.li@amd.com>
Tested-by: default avatarDan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8397f38d

drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h

+11 −0
Original line number Diff line number Diff line
@@ -49,6 +49,11 @@ enum dml2_source_format_class { 
	dml2_422_packed_12 = 18

};



enum dml2_sample_positioning {

	dml2_interstitial = 0,

	dml2_cosited = 1

};



enum dml2_rotation_angle {

	dml2_rotation_0 = 0,

	dml2_rotation_90 = 1,
@@ -222,7 +227,11 @@ struct dml2_composition_cfg { 


	struct {

		bool enabled;

		bool easf_enabled;

		bool isharp_enabled;

		bool upsp_enabled;

		enum dml2_sample_positioning upsp_sample_positioning;

		unsigned int upsp_vtaps;

		struct {

			double h_ratio;

			double v_ratio;
@@ -385,6 +394,7 @@ struct dml2_plane_parameters { 
		// The actual reserved vblank time used for the corresponding stream in mode_programming would be at least as much as this per-plane override.

		long reserved_vblank_time_ns;

		unsigned int max_vactive_det_fill_delay_us; // 0 = no reserved time, +ve = explicit max delay

		unsigned int vactive_latency_to_hide_for_pstate_admissibility_us;

		unsigned int gpuvm_min_page_size_kbytes;

		unsigned int hostvm_min_page_size_kbytes;
@@ -456,6 +466,7 @@ struct dml2_display_cfg { 
				bool enable;

				bool value;

			} force_nom_det_size_kbytes;



			bool mode_support_check_disable;

			bool mcache_admissibility_check_disable;

			bool surface_viewport_size_check_disable;

drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_soc_parameter_types.h

+6 −1
Original line number Diff line number Diff line
@@ -145,6 +145,8 @@ struct dml2_soc_bb { 
	struct dml2_soc_vmin_clock_limits vmin_limit;



	double lower_bound_bandwidth_dchub;

	double fraction_of_urgent_bandwidth_nominal_target;

	double fraction_of_urgent_bandwidth_flip_target;

	unsigned int dprefclk_mhz;

	unsigned int xtalclk_mhz;

	unsigned int pcie_refclk_mhz;
@@ -170,6 +172,7 @@ struct dml2_soc_bb { 
struct dml2_ip_capabilities {

	unsigned int pipe_count;

	unsigned int otg_count;

	unsigned int TDLUT_33cube_count;

	unsigned int num_dsc;

	unsigned int max_num_dp2p0_streams;

	unsigned int max_num_hdmi_frl_outputs;
@@ -188,7 +191,9 @@ struct dml2_ip_capabilities { 
	unsigned int subvp_prefetch_end_to_mall_start_us;

	unsigned int subvp_fw_processing_delay;

	unsigned int max_vactive_det_fill_delay_us;



	unsigned int ppt_max_allow_delay_ns;

	unsigned int temp_read_max_allow_delay_us;

	unsigned int dummy_pstate_max_allow_delay_us;

	/* FAMS2 delays */

	struct {

		unsigned int max_allow_delay_us;

drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

+13 −0
Original line number Diff line number Diff line
@@ -70,6 +70,8 @@ struct dml2_pmo_options { 
	bool disable_dyn_odm;

	bool disable_dyn_odm_for_multi_stream;

	bool disable_dyn_odm_for_stream_with_svp;

	struct dml2_pmo_pstate_strategy *override_strategy_lists[DML2_MAX_PLANES];

	unsigned int num_override_strategies_per_list[DML2_MAX_PLANES];

};



struct dml2_options {
@@ -193,6 +195,14 @@ struct dml2_mcache_surface_allocation { 
	} informative;

};



enum dml2_pstate_type {

	dml2_pstate_type_uclk,

	dml2_pstate_type_ppt,

	dml2_pstate_type_temp_read,

	dml2_pstate_type_dummy_pstate,

	dml2_pstate_type_count

};



enum dml2_pstate_method {

	dml2_pstate_method_na = 0,

	/* hw exclusive modes */
@@ -310,6 +320,7 @@ struct dml2_mode_support_info { 
	bool NumberOfOTGSupport;

	bool NumberOfHDMIFRLSupport;

	bool NumberOfDP2p0Support;

	bool NumberOfTDLUT33cubeSupport;

	bool WritebackScaleRatioAndTapsSupport;

	bool CursorSupport;

	bool PitchSupport;
@@ -357,6 +368,8 @@ struct dml2_mode_support_info { 
	unsigned int AlignedCPitch[DML2_MAX_PLANES];

	bool g6_temp_read_support;

	bool temp_read_or_ppt_support;

	bool qos_bandwidth_support;

	bool dcfclk_support;

}; // dml2_mode_support_info



struct dml2_display_cfg_programming {

drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

+29 −26
Original line number Diff line number Diff line
@@ -12756,7 +12756,7 @@ void dml2_core_calcs_get_stream_fams2_programming(const struct dml2_core_interna 
{

	const struct dml2_plane_parameters *plane_descriptor = &display_cfg->display_config.plane_descriptors[plane_index];

	const struct dml2_stream_parameters *stream_descriptor = &display_cfg->display_config.stream_descriptors[plane_descriptor->stream_index];

	const struct dml2_fams2_meta *stream_fams2_meta = &display_cfg->stage3.stream_fams2_meta[plane_descriptor->stream_index];

	const struct dml2_pstate_meta *stream_pstate_meta = &display_cfg->stage3.stream_pstate_meta[plane_descriptor->stream_index];









	struct dmub_fams2_cmd_stream_static_base_state *base_programming = &fams2_base_programming->stream_v1.base;









	union dmub_fams2_cmd_stream_static_sub_state *sub_programming = &fams2_sub_programming->stream_v1.sub_state;








@@ -12771,24 +12771,24 @@ void dml2_core_calcs_get_stream_fams2_programming(const struct dml2_core_interna







	/* from display configuration */









	base_programming->htotal = (uint16_t)stream_descriptor->timing.h_total;









	base_programming->vtotal = (uint16_t)stream_descriptor->timing.v_total;









	base_programming->vblank_start = (uint16_t)(stream_fams2_meta->nom_vtotal -









	base_programming->vblank_start = (uint16_t)(stream_pstate_meta->nom_vtotal -









		stream_descriptor->timing.v_front_porch);









	base_programming->vblank_end = (uint16_t)(stream_fams2_meta->nom_vtotal -









	base_programming->vblank_end = (uint16_t)(stream_pstate_meta->nom_vtotal -









		stream_descriptor->timing.v_front_porch -









		stream_descriptor->timing.v_active);









	base_programming->config.bits.is_drr = stream_descriptor->timing.drr_config.enabled;

















	/* from meta */









	base_programming->otg_vline_time_ns =









		(unsigned int)(stream_fams2_meta->otg_vline_time_us * 1000.0);









	base_programming->scheduling_delay_otg_vlines = (uint8_t)stream_fams2_meta->scheduling_delay_otg_vlines;









	base_programming->contention_delay_otg_vlines = (uint8_t)stream_fams2_meta->contention_delay_otg_vlines;









	base_programming->vline_int_ack_delay_otg_vlines = (uint8_t)stream_fams2_meta->vertical_interrupt_ack_delay_otg_vlines;









	base_programming->drr_keepout_otg_vline = (uint16_t)(stream_fams2_meta->nom_vtotal -









		(unsigned int)(stream_pstate_meta->otg_vline_time_us * 1000.0);









	base_programming->scheduling_delay_otg_vlines = (uint8_t)stream_pstate_meta->scheduling_delay_otg_vlines;









	base_programming->contention_delay_otg_vlines = (uint8_t)stream_pstate_meta->contention_delay_otg_vlines;









	base_programming->vline_int_ack_delay_otg_vlines = (uint8_t)stream_pstate_meta->vertical_interrupt_ack_delay_otg_vlines;









	base_programming->drr_keepout_otg_vline = (uint16_t)(stream_pstate_meta->nom_vtotal -









		stream_descriptor->timing.v_front_porch -









		stream_fams2_meta->method_drr.programming_delay_otg_vlines);









	base_programming->allow_to_target_delay_otg_vlines = (uint8_t)stream_fams2_meta->allow_to_target_delay_otg_vlines;









	base_programming->max_vtotal = (uint16_t)stream_fams2_meta->max_vtotal;









		stream_pstate_meta->method_drr.programming_delay_otg_vlines);









	base_programming->allow_to_target_delay_otg_vlines = (uint8_t)stream_pstate_meta->allow_to_target_delay_otg_vlines;









	base_programming->max_vtotal = (uint16_t)stream_pstate_meta->max_vtotal;

















	/* from core */









	base_programming->config.bits.min_ttu_vblank_usable = true;








@@ -12807,11 +12807,11 @@ void dml2_core_calcs_get_stream_fams2_programming(const struct dml2_core_interna







		/* legacy vactive */









		base_programming->type = FAMS2_STREAM_TYPE_VACTIVE;









		sub_programming->legacy.vactive_det_fill_delay_otg_vlines =









			(uint8_t)stream_fams2_meta->method_vactive.max_vactive_det_fill_delay_otg_vlines;









			(uint8_t)stream_pstate_meta->method_vactive.max_vactive_det_fill_delay_otg_vlines;









		base_programming->allow_start_otg_vline =









			(uint16_t)stream_fams2_meta->method_vactive.common.allow_start_otg_vline;









			(uint16_t)stream_pstate_meta->method_vactive.common.allow_start_otg_vline;









		base_programming->allow_end_otg_vline =









			(uint16_t)stream_fams2_meta->method_vactive.common.allow_end_otg_vline;









			(uint16_t)stream_pstate_meta->method_vactive.common.allow_end_otg_vline;









		base_programming->config.bits.clamp_vtotal_min = true;









		break;









	case dml2_pstate_method_vblank:








@@ -12819,22 +12819,22 @@ void dml2_core_calcs_get_stream_fams2_programming(const struct dml2_core_interna







		/* legacy vblank */









		base_programming->type = FAMS2_STREAM_TYPE_VBLANK;









		base_programming->allow_start_otg_vline =









			(uint16_t)stream_fams2_meta->method_vblank.common.allow_start_otg_vline;









			(uint16_t)stream_pstate_meta->method_vblank.common.allow_start_otg_vline;









		base_programming->allow_end_otg_vline =









			(uint16_t)stream_fams2_meta->method_vblank.common.allow_end_otg_vline;









			(uint16_t)stream_pstate_meta->method_vblank.common.allow_end_otg_vline;









		base_programming->config.bits.clamp_vtotal_min = true;









		break;









	case dml2_pstate_method_fw_drr:









		/* drr */









		base_programming->type = FAMS2_STREAM_TYPE_DRR;









		sub_programming->drr.programming_delay_otg_vlines =









			(uint8_t)stream_fams2_meta->method_drr.programming_delay_otg_vlines;









			(uint8_t)stream_pstate_meta->method_drr.programming_delay_otg_vlines;









		sub_programming->drr.nom_stretched_vtotal =









			(uint16_t)stream_fams2_meta->method_drr.stretched_vtotal;









			(uint16_t)stream_pstate_meta->method_drr.stretched_vtotal;









		base_programming->allow_start_otg_vline =









			(uint16_t)stream_fams2_meta->method_drr.common.allow_start_otg_vline;









			(uint16_t)stream_pstate_meta->method_drr.common.allow_start_otg_vline;









		base_programming->allow_end_otg_vline =









			(uint16_t)stream_fams2_meta->method_drr.common.allow_end_otg_vline;









			(uint16_t)stream_pstate_meta->method_drr.common.allow_end_otg_vline;









		/* drr only clamps to vtotal min for single display */









		base_programming->config.bits.clamp_vtotal_min = display_cfg->display_config.num_streams == 1;









		sub_programming->drr.only_stretch_if_required = true;








@@ -12847,13 +12847,13 @@ void dml2_core_calcs_get_stream_fams2_programming(const struct dml2_core_interna







			(uint16_t)(plane_descriptor->composition.scaler_info.plane0.v_ratio * 1000.0);









		sub_programming->subvp.vratio_denominator = 1000;









		sub_programming->subvp.programming_delay_otg_vlines =









			(uint8_t)stream_fams2_meta->method_subvp.programming_delay_otg_vlines;









			(uint8_t)stream_pstate_meta->method_subvp.programming_delay_otg_vlines;









		sub_programming->subvp.prefetch_to_mall_otg_vlines =









			(uint8_t)stream_fams2_meta->method_subvp.prefetch_to_mall_delay_otg_vlines;









			(uint8_t)stream_pstate_meta->method_subvp.prefetch_to_mall_delay_otg_vlines;









		sub_programming->subvp.phantom_vtotal =









			(uint16_t)stream_fams2_meta->method_subvp.phantom_vtotal;









			(uint16_t)stream_pstate_meta->method_subvp.phantom_vtotal;









		sub_programming->subvp.phantom_vactive =









			(uint16_t)stream_fams2_meta->method_subvp.phantom_vactive;









			(uint16_t)stream_pstate_meta->method_subvp.phantom_vactive;









		sub_programming->subvp.config.bits.is_multi_planar =









			plane_descriptor->surface.plane1.height > 0;









		sub_programming->subvp.config.bits.is_yuv420 =








@@ -12862,9 +12862,9 @@ void dml2_core_calcs_get_stream_fams2_programming(const struct dml2_core_interna







			plane_descriptor->pixel_format == dml2_420_12;

















		base_programming->allow_start_otg_vline =









			(uint16_t)stream_fams2_meta->method_subvp.common.allow_start_otg_vline;









			(uint16_t)stream_pstate_meta->method_subvp.common.allow_start_otg_vline;









		base_programming->allow_end_otg_vline =









			(uint16_t)stream_fams2_meta->method_subvp.common.allow_end_otg_vline;









			(uint16_t)stream_pstate_meta->method_subvp.common.allow_end_otg_vline;









		base_programming->config.bits.clamp_vtotal_min = true;









		break;









	case dml2_pstate_method_reserved_hw:








@@ -13027,7 +13027,10 @@ void dml2_core_calcs_get_informative(const struct dml2_core_internal_display_mod







	out->informative.mode_support_info.VRatioInPrefetchSupported = mode_lib->ms.support.VRatioInPrefetchSupported;









	out->informative.mode_support_info.DISPCLK_DPPCLK_Support = mode_lib->ms.support.DISPCLK_DPPCLK_Support;









	out->informative.mode_support_info.TotalAvailablePipesSupport = mode_lib->ms.support.TotalAvailablePipesSupport;









	out->informative.mode_support_info.NumberOfTDLUT33cubeSupport = mode_lib->ms.support.NumberOfTDLUT33cubeSupport;









	out->informative.mode_support_info.ViewportSizeSupport = mode_lib->ms.support.ViewportSizeSupport;









	out->informative.mode_support_info.qos_bandwidth_support = mode_lib->ms.support.qos_bandwidth_support;









	out->informative.mode_support_info.dcfclk_support = mode_lib->ms.support.dcfclk_support;

















	for (k = 0; k < out->display_config.num_planes; k++) {

































drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c



+2
−0






























Original line number
Diff line number
Diff line







@@ -15,6 +15,8 @@ bool dml2_core_create(enum dml2_project_id project_id, struct dml2_core_instance

















	memset(out, 0, sizeof(struct dml2_core_instance));



















	out->project_id = project_id;



















	switch (project_id) {









	case dml2_project_dcn4x_stage1:









		result = false;