Commit 0981e0ef authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/gfx12: add support for disable_kq 



Plumb in support for disabling kernel queues.

v2: use ring counts per Felix' suggestion
v3: fix stream fault handler, enable EOP interrupts
v4: fix MEC interrupt offset (Sunil)
v5: clean up after removing extra sched.ready settings

Reviewed-by: default avatarSunil Khatri <sunil.khatri@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1e63ebc0

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

+114 −53
Original line number Diff line number Diff line
@@ -1442,11 +1442,13 @@ static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block) 
		break;

	}



	if (adev->gfx.num_compute_rings) {

		/* recalculate compute rings to use based on hardware configuration */

		num_compute_rings = (adev->gfx.mec.num_pipe_per_mec *

				     adev->gfx.mec.num_queue_per_pipe) / 2;

		adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings,

						  num_compute_rings);

	}



	/* EOP Event */

	r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
@@ -1492,6 +1494,7 @@ static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block) 
		return r;

	}



	if (adev->gfx.num_gfx_rings) {

		/* set up the gfx ring */

		for (i = 0; i < adev->gfx.me.num_me; i++) {

			for (j = 0; j < num_queue_per_pipe; j++) {
@@ -1507,7 +1510,9 @@ static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block) 
				}

			}

		}

	}



	if (adev->gfx.num_compute_rings) {

		ring_id = 0;

		/* set up the compute queues - allocate horizontally across pipes */

		for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
@@ -1526,6 +1531,7 @@ static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block) 
				}

			}

		}

	}



	adev->gfx.gfx_supported_reset =

		amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]);
@@ -3671,6 +3677,46 @@ static int gfx_v12_0_hw_init(struct amdgpu_ip_block *ip_block) 
	return r;

}



static int gfx_v12_0_set_userq_eop_interrupts(struct amdgpu_device *adev,

					      bool enable)

{

	if (adev->gfx.disable_kq) {

		unsigned int irq_type;

		int m, p, r;



		for (m = 0; m < adev->gfx.me.num_me; m++) {

			for (p = 0; p < adev->gfx.me.num_pipe_per_me; p++) {

				irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p;

				if (enable)

					r = amdgpu_irq_get(adev, &adev->gfx.eop_irq,

							   irq_type);

				else

					r = amdgpu_irq_put(adev, &adev->gfx.eop_irq,

							   irq_type);

				if (r)

					return r;

			}

		}



		for (m = 0; m < adev->gfx.mec.num_mec; ++m) {

			for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) {

				irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP

					+ (m * adev->gfx.mec.num_pipe_per_mec)

					+ p;

				if (enable)

					r = amdgpu_irq_get(adev, &adev->gfx.eop_irq,

							   irq_type);

				else

					r = amdgpu_irq_put(adev, &adev->gfx.eop_irq,

							   irq_type);

				if (r)

					return r;

			}

		}

	}

	return 0;

}



static int gfx_v12_0_hw_fini(struct amdgpu_ip_block *ip_block)

{

	struct amdgpu_device *adev = ip_block->adev;
@@ -3681,6 +3727,7 @@ static int gfx_v12_0_hw_fini(struct amdgpu_ip_block *ip_block) 
	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);

	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);

	amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0);

	gfx_v12_0_set_userq_eop_interrupts(adev, false);



	if (!adev->no_hw_access) {

		if (amdgpu_async_gfx_ring) {
@@ -3769,11 +3816,19 @@ static int gfx_v12_0_early_init(struct amdgpu_ip_block *ip_block) 
{

	struct amdgpu_device *adev = ip_block->adev;



	if (amdgpu_disable_kq == 1)

		adev->gfx.disable_kq = true;



	adev->gfx.funcs = &gfx_v12_0_gfx_funcs;



	if (adev->gfx.disable_kq) {

		adev->gfx.num_gfx_rings = 0;

		adev->gfx.num_compute_rings = 0;

	} else {

		adev->gfx.num_gfx_rings = GFX12_NUM_GFX_RINGS;

		adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),

						  AMDGPU_MAX_COMPUTE_RINGS);

	}



	gfx_v12_0_set_kiq_pm4_funcs(adev);

	gfx_v12_0_set_ring_funcs(adev);
@@ -3804,6 +3859,10 @@ static int gfx_v12_0_late_init(struct amdgpu_ip_block *ip_block) 
	if (r)

		return r;



	r = gfx_v12_0_set_userq_eop_interrupts(adev, true);

	if (r)

		return r;



	return 0;

}
@@ -4935,6 +4994,7 @@ static void gfx_v12_0_handle_priv_fault(struct amdgpu_device *adev, 
	pipe_id = (entry->ring_id & 0x03) >> 0;

	queue_id = (entry->ring_id & 0x70) >> 4;



	if (!adev->gfx.disable_kq) {

		switch (me_id) {

		case 0:

			for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
@@ -4958,6 +5018,7 @@ static void gfx_v12_0_handle_priv_fault(struct amdgpu_device *adev, 
			break;

		}

	}

}



static int gfx_v12_0_priv_reg_irq(struct amdgpu_device *adev,

				  struct amdgpu_irq_src *source,